參數(shù)資料
型號: ADS8616A8A-75
廠商: ADATA Technology Co., Ltd.
英文描述: Synchronous DRAM(4M X 16 Bit X 4 Banks)
中文描述: 同步DRAM(4米× 16位× 4個銀行)
文件頁數(shù): 1/8頁
文件大小: 550K
代理商: ADS8616A8A-75
A-Data
ADS8616A8A
Synchronous DRAM
4M x 16 Bit x 4 Banks
General Description
The ADS8616A8A are four-bank Synchronous
DRAMs organized as 4,194,304 words x 16 bits x 4
banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
Features
JEDEC standard LVTTL 3.3V power supply
MRS Cycle with address key programs
-CAS Latency (2 & 3)
-Burst Length (1,2,4,8,& full page)
-Burst Type (sequential & Interleave)
4 banks operation
All inputs are sampled at the positive edge of
the system clock
Burst Read single write operation
Auto & Self refresh
DQM for masking
8192 Refresh Cycles
Package:54-pins 400 mil TSOP-Type II
Ordering Information.
Part No.
Frequency
Interface
Package
ADS8616A8A-75
133Mhz-333
LVTTL
400mil 54pin TSOPII
ADS8616A8A-75A
133Mhz-222
LVTTL
400mil 54pin TSOPII
Pin Assignment
54
53
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
52
51
50
49
48
47
46
45
44
43
36
37
35
34
33
41
42
40
39
38
32
31
30
29
Vss
DQ7
Vss
Q
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
V
SS
NC/RFU
DQM
CK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
V
DD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
54-pin plastic TSOP II 400 mil
Rev 1.0 December, 2001
1
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