參數(shù)資料
型號: ADS7864M-EVM
廠商: Texas Instruments
文件頁數(shù): 11/27頁
文件大?。?/td> 0K
描述: EVAL MODULE FOR ADS7864M
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標準包裝: 1
ADC 的數(shù)量: 2
位數(shù): 12
采樣率(每秒): 500k
數(shù)據(jù)接口: 并聯(lián)
輸入范圍: 0 ~ 5 V
在以下條件下的電源(標準): 50mW @ 500kSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: ADS7864
已供物品:
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ADS7864Y/250G4-ND - IC 12BIT 500KHZ 6CH ADC 48-TQFP
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ADS7864YBTR-ND - IC 12BIT 500KHZ 6CH A/D 48-TQFP
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更多...
其它名稱: 296-30697
ADS7864M-EVM-ND
www.ti.com
RESET
BUSY
Conversion
Channel A
empty
Conversion
Channel B
Conversion
Channel C
RD
t
0
t
1
t
2
t
3
reg. 5
reg. 4
reg. 2
reg. 3
reg. 1
reg. 0
empty
ch A1
ch A0
empty
ch B1
ch B0
ch A1
empty
ch A1
empty
ch C1
ch C0
ch B1
ch B0
ch A1
t
4
ADS7864
SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005
At time tB a HOLDB signal occurs. With the next
Bit 15 shows if the FIFO is empty (low) or if it
falling clock edge (tC) the ADS7864 puts channel B
contains channel information (high). Bits 12 to 14
into the loop to be converted next. As the reset signal
contain the Channel for the 12-bit data word (Bit 0 to
occurred at tA, the conversion of channel B will be
11). If the data is from channel A0, then bits 14 to 12
started with the next rising edge of the clock after tC.
are ‘000’. The Channel bit pattern is outlined in
Table 2 (Channel Truth Table).
Within the next clock cycle (tC to tF), HOLDC (tD) and
HOLDA (tE) occur. If more than one hold signals get
New data is always written into the next available
active within one clock cycle, channel A will be
register. At t0 (see Figure 32), the reset deletes all the
converted first. Therefore, as soon as the conversion
existing data. At t1 the new data of the channels A0
of channel B is done, the conversion of channel A will
and A1 are put into registers 0 and 1. On t2 the read
be initiated. After this second conversion, channel C
process of channel A0 data is finished. Therefore,
will be converted.
this data is dumped and A1 data is shifted to register
0. At t3 new data is available, this time from channel
The 16 bit output word has following structure:
B0 and B1. This data is written into the next available
3-Bit Channel
registers (register 1 and 2). The new data of channel
Valid Data
12-Bit Data Word
Information
C0 and C1 at t4 is put on top (registers 3 and 4).
Figure 32. Functionality Diagram of FIFO Registers
19
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ADS7864Y/250G4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 500kHz 12-Bit 6-Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS7864Y/2K 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 500kHz 12-Bit 6-Ch Simltns Smplng ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32