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參數(shù)資料
型號： ADS7864YB/2K
廠商： Texas Instruments
文件頁數(shù)： 10/27頁
文件大?。?/td> 0K
描述： IC 12BIT 500KHZ 6CH A/D 48-TQFP
產(chǎn)品培訓模塊： Data Converter Basics
標準包裝： 2,000
位數(shù)： 12
采樣率（每秒）： 500k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 50mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 12 個單端，雙極；6 個差分，雙極
配用： 296-30697-ND - EVAL MODULE FOR ADS7864M
www.ti.com
GETTING DATA
RESET
CLOCK
HOLDA
HOLDB
HOLDC
t
A
t
B
t
C
t
D tE
t
F
ADS7864
SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005
from channel A0 is read on the first RD signal, then
A1 on the second, followed by B0, B1, C0 and finally
The ADS7864 has three different output modes that
C1 before reading A0 again. Data from channel A0 is
are selected with A2, A1 and A0. A2A1A0 are only
brought to the output first after a reset-signal or after
active when RD and CS are both low. After a reset
powering the part up.
occurs, A2A1A0 are set to 000.
The third mode is a FIFO mode that is addressed
With (A2 A1 A0) = 000 to 101 a particular channel
with (A2 A1 A0 = 111). Data of the channel that is
can directly be addressed (see Table 3 and Fig-
converted first will be read first. So, if a particular
ure 27). The channel address should be set at least
channel is most interesting and is converted more
10ns (see Figure 28, t12) before the falling edge of
frequently (e.g., to get a history of a particular
RD and should not change as long as RD is low.
channel) then there are three output registers per
channel available to store data. When the ADS7864
Table 3. Address/Mode Truth Table
is operated in the FIFO mode, an initial RD/CS is
CHANNEL
necessary (after power up and after reset), so that
SELECTED/
the internal address is set to ‘111’, before the first
MODE
A2
A1
A0
conversion starts.
A0
0
If a read process is just going on (RD signal low) and
A1
0
1
new data has to be stored, then the ADS7864 will
B0
0
1
0
wait until the read process is finished (RD signal
B1
0
1
going high) before the new data gets latched into its
output register.
C0
1
0
C1
1
0
1
At time tA (see Figure 31) the ADS7864 resets. With
Cycle Mode
1
0
the reset signal, all conversions and scheduled con-
versions are cancelled. The data in the output regis-
FIFO Mode
1
ters are also cleared. With a reset, a running conver-
With (A2 A1 A0) = 110 the interface is running in a
sion gets interrupted and all channels go into the
cycle mode (see Figure 29 and Figure 30). Here, data
sample mode again.
Figure 31. Example of Hold Signals
18
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