t4 t10
參數(shù)資料
型號(hào): ADS7864YB/2K
廠商: Texas Instruments
文件頁(yè)數(shù): 8/27頁(yè)
文件大小: 0K
描述: IC 12BIT 500KHZ 6CH A/D 48-TQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 12
采樣率(每秒): 500k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 50mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP
供應(yīng)商設(shè)備封裝: 48-TQFP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 12 個(gè)單端,雙極;6 個(gè)差分,雙極
配用: 296-30697-ND - EVAL MODULE FOR ADS7864M
www.ti.com
BUSY
CLOCK
HOLDB
CS
RD
A0
t4
t10
t11
BUSY
CLOCK
HOLDB
CS
RD
A0
t
4
t
1
t
13
t
14
t
12
ADS7864
SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005
Figure 27. Timing of One Conversion Cycle
READING DATA (RD, CS)—In general, the chan-
nel/data outputs are in tristate. Both CS and RD have
to be low to enable these outputs. RD and CS have
to stay low together for at least 30ns (see Figure 28,
t13) before the output data is valid. RD has to remain
high for at least 30ns (see Figure 28, t14) before
bringing it back low for a subsequent read command.
12.5 clock-cycles after the start of a conversion
(BUSY going low), the new data is latched into its
output register. If a read process is initiated around
12.5 clock cycles after BUSY went low, RD and CS
should stay low for at least 50ns to get the new data
stored to its register and switched to the output.
CS being low tells the ADS7864 that the bus on the
board is assigned to the ADS7864. If an A/D con-
verter shares a bus with digital gates, there is a
possibility that digital (high frequency) noise may be
coupled into the A/D converter. If the bus is just used
by the ADS7864, CS can be hardwired to ground.
Reading data at the falling edge of one of the hold
signals might cause distortion of the hold value.
Figure 28. Timing for Reading Data
16
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