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參數(shù)資料
| 型號： | ADS8361IRHBTG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 26/29頁 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 16BIT 500KSPS 32VQFN |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 200mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，雙極；4 個差分，雙極 |
| 配用： | 296-19922-ND - EVAL MOD FOR ADS8361 296-18350-ND - KIT 5-6K INTERFACE BOARD |
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ADS8361
6
SBAS230E
www.ti.com
PIN CONFIGURATION
Top View
SSOP
BGND
CH B1+
CH B1–
CH B0+
CH B0–
CH A1+
CH A1–
CH A0+
CH A0–
REFIN
REFOUT
AGND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
BVDD
SERIAL DATA A
SERIAL DATA B
BUSY
CLOCK
CS
RD
CONVST
A0
M0
M1
AVDD
ADS8361
Top View
QFN
SSOP QFN
PIN
NAME
DESCRIPTION
128
BGND
Digital I/O Ground. Connect directly to analog ground (pin 12).
2
1
CH B1+
Noninverting Input Channel B1
3
2
CH B1–
Inverting Input Channel B1
4
3
CH B0+
Noninverting Input Channel B0
5
4
CH B0–
Inverting Input Channel B0
6
5
CH A1+
Noninverting Input Channel A1
7
6
CH A1–
Inverting Input Channel A1
8
7
CH A0+
Noninverting Input Channel A0
9
8
CH A0–
Inverting Input Channel A0
10
9
REFIN
Reference Input
11
10
REFOUT
2.5V Reference Output
12
AGND
Analog Ground. Connect directly to digital ground (pin 1).
13
AVDD
Analog Power Supply, +5VDC. Decouple to analog ground with a 0.1μF ceramic capacitor and a 10μF tantalum capacitor.
14
16
M1
Selects between the Serial Outputs. When M1 is LOW, both Serial Output A and Serial Output B are selected for data transfer. When M1
is HIGH, Serial output A is configured for both Channel A data and Channel B data; Serial Output B goes into tri-state (i.e., high impedance).
15
17
M0
Selects between two-channel and four-channel operation. When M0 is LOW, two-channel operation is selected and operates in
conjunction with A0. When A0 is HIGH, Channel A1 and Channel B1 are being converted. When A0 is LOW, Channel A0 and Channel
B0 are being converted. When M0 is HIGH, four-channel operation is selected. In this mode, all four channels are converted in sequence
starting with Channels A0 and B0, followed by Channels A1 and B1.
16
18
A0
A0 operates in conjunction with M0. With M0 LOW and A0 HIGH, Channel A1 and Channel B1 are converted. With M0 LOW and A0 LOW,
Channel A0 and Channel B0 are converted.
17
19
CONVST Convert Start. When CONVST switches from LOW to HIGH, the device switches from the sample to hold mode, independent of the status
of the external clock.
18
20
RD
Synchronization Pulse for the Serial Output.
19
21
CS
Chip Select. When LOW, the Serial Output A and Serial Output B outputs are active; when HIGH, the serial outputs are tri-stated.
20
22
CLOCK
An external CMOS-compatible clock can be applied to the CLOCK input to synchronize the conversion process to an external source.
The CLOCK pin controls the sampling rate by the equation: fSAMPLE (max) = CLOCK/20.
21
23
BUSY
BUSY goes HIGH during a conversion and returns LOW after the third LSB has been transmitted on either the Serial A or Serial B output
pin.
22
24
SERIAL
The Serial Output data word is comprised of channel information and 16 bits of data. In operation, data is valid on the falling edge of
DCLOCK for 20 edges after the rising edge of RD.
23
25
SERIAL
The Serial Output data word is comprised of channel information and 16 bits of data. In operation, data is valid on the falling edge of
DCLOCK for 20 edges after the rising edge of RD. When M1 is HIGH, both Channel A data and Channel B data are available.
24
27
BVDD
Digital I/O Power Supply, 2.7V to 5.5V
PIN DESCRIPTIONS
DATA B
DATA A
CH B1+
CH B1
CH B0+
CH B0
CH A1+
CH A1
CH A0+
CH A0
SERIAL DATA B
BUSY
CLOCK
CS
RD
CONVST
A0
M0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
ADS8361(1)
NC
(2)
NC
(2)
NC
(2)
NC
(2)
BGND
BVDD
NC
(2)
SERIAL
DATA
A
32
31
30
29
28
27
26
25
REF
IN
REF
OUT
NC
(2)
AGND
AV
DD
NC
(2)
NC
(2)
M1
9
10
11
12
13
14
15
16
NOTE: (1) The thermal pad is internally connected to the substrate.
This pad can be connected to the analog ground or left floating.
Keep the thermal pad separate from the digital ground, if possible.
(2) NC = Not Connected.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS8363 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Dual, 1MSPS, 16-/14-/12-Bit, 4x2 or 2x2 Channel, Simultaneous Sampling Analog-to-Digital Converter |
| ADS8363EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS8363 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS8363SRHBR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16B 1MSPS 4x2/2x2 Simu Sampling SAR RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8363SRHBT | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16B 1MSPS 4x2/2x2 Simu Sampling SAR RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8364 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:250kHz, 16-Bit, 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS |
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