參數(shù)資料
型號: ADS8365IPAGRG4
英文描述: 16-Bit, 250kSPS, 6-Channel, Simultaneous Sampling SAR ANALOG-TO-DIGITAL CONVERTERS
中文描述: 16位,AD7691的6通道同步采樣SAR類比數(shù)位轉(zhuǎn)換器
文件頁數(shù): 18/33頁
文件大?。?/td> 441K
代理商: ADS8365IPAGRG4
www.ti.com
BIPOLAR INPUTS
The
differential
designed to accept bipolar inputs (–V
REF
and +V
REF
)
around the common-mode voltage (2.5V), which
corresponds to a 0V to 5V input range with a 2.5V
reference. By using a simple op amp circuit featuring
four, high-precision external resistors, the ADS8365
can be configured to accept a bipolar input range.
The conventional
±
2.5V,
±
5V, and
±
10V input ranges
could be interfaced to the ADS8365 using the
resistor values shown in
Figure 26
.
TRANSITION NOISE
The transition noise of the ADS8365 itself is low, as
shown
in
Figure
25
These
generated by applying a low-noise dc input and
initiating 8000 conversions. The digital output of the
ADC will vary in output code due to the internal noise
of the ADS8365; this feature is true for all 16-bit,
successive approximation register (SAR) type ADCs.
Using a histogram to plot the output codes, the
distribution should appear bell-shaped, with the peak
of the bell curve representing the nominal code for
the input value. The
±
1
σ
,
±
2
σ
, and
±
3
σ
distributions
represent
the
68.3%,
respectively, of all codes. The transition noise can be
calculated
by
dividing
measured by 6, yielding the
±
3
σ
distribution, or
99.7%, of all codes. Statistically, up to three codes
could fall outside the distribution when executing
1000 conversions. Remember, in order to achieve
this low-noise performance, the peak-to-peak noise
of the input signal and reference must be < 50
μ
V.
R
1
R
2
+IN
-
IN
REF
(pin 61)
OUT
2.5V
4k
W
20k
W
Bipolar
Input
BIPOLAR INPUT
R
1
R
2
±
10V
1k
W
5k
W
±
5V
2k
W
10k
W
±
2.5V
4k
W
20k
W
OPA227
ADS8365
OPA227
1.2k
W
1.2k
W
TIMING AND CONTROL
The ADS8365 uses an external clock (CLK, pin 28)
that controls the conversion rate of the CDAC. With a
5MHz external clock, the ADC sampling rate is
250kSPS which corresponds to a 4
μ
s maximum
throughput time. Acquisition and conversion take a
total of 20 clock cycles.
0
5 0
1000
1500
2000
2500
3000
3500
4000
32782
32783
32784
32785
32786
32787
Code
O
42
649
3379
603
37
3290
ADS8365
SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006
charges the internal capacitor array during the
sampling period. After this capacitance has been
fully charged, there is no further input current. The
source of the analog input voltage must be able to
charge the input capacitance (25pF) to a 16-bit
settling level within three clock cycles if the minimum
acquisition time is used. When the converter goes
into the hold mode, the input impedance is greater
than 1G
. Care must be taken regarding the
absolute analog input voltage. The +IN and –IN
inputs should always remain within the range of
AGND – 0.3V to AV
DD
+ 0.3V.
The
OPA365
is a good choice for driving the analog
inputs in a 5V, single-supply application.
inputs
of
the
ADS8365
were
histograms
were
95.5%,
and
99.7%,
Figure 26. Level Shift Circuit for Bipolar Input
Ranges
the
number
of
codes
Figure 25. 8000 Conversion Histogram of a DC
Input
18
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