- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19376 > ADSP-21061KSZ-133 (Analog Devices Inc)IC DSP CONTROLLER 32BIT 240MQFP PDF資料下載
參數(shù)資料
| 型號： | ADSP-21061KSZ-133 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 240MQFP |
| 產(chǎn)品培訓(xùn)模塊： | SHARC Processor Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | 同步串行端口（SSP） |
| 時(shí)鐘速率： | 33MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 128kB |
| 電壓 - 輸入/輸出： | 5.00V |
| 電壓 - 核心： | 5.00V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BFQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 240-MQFP-EP（32x32） |
| 包裝： | 托盤 |
第1頁當(dāng)前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
Rev. D | Page 10 of 52 | May 2013
ACK
I/O/S
Memory Acknowledge.
External devices can deassert ACK (low) to add wait states to an external memory
access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an
external memory access. The ADSP-21061 deasserts ACK as an output to add wait states to a synchronous
access of its internal memory. In a multiprocessing system, a slave ADSP-21061 deasserts the bus master’s
ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its
ACK pin that maintains the input at the level to which it was last driven.
SBTS
I/S
Suspend Bus Three-State.
External devices can assert SBTS (low) to place the external bus address, data,
selects, and strobes in a high impedance state for the following cycle. If the ADSP-21061 attempts to access
external memory while SBTS is asserted, the processor halts and the memory access is not complete until
SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-21061 deadlock, or used
with a DRAM controller.
IRQ2–0
I/A
Interrupt Request Lines.
May be either edge-triggered or level-sensitive.
FLAG3–0
I/O/A
Flag Pins.
Each is configured via control bits as either an input or output. As an input, they can be tested as
a condition. As an output, they can be used to signal external peripherals.
TIMEXP
O
Timer Expired.
Asserted for four cycles when the timer is enabled and TCOUNT decrements to zero.
HBR
I/A
Host Bus Request.
This pin must be asserted by a host processor to request control of the ADSP-21061’s
external bus. When HBR is asserted in a multiprocessing system, the ADSP-21061 that is bus master will
relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21061 places the address, data, select,
and strobe lines in a high impedance state. HBR has priority over all ADSP-21061 bus requests BR6–1 in a
multiprocessing system.
HBG
I/O
Host Bus Grant.
Acknowledges a bus request, indicating that the host processor may take control of the
externalbus.HBGisasserted(heldlow)bytheADSP-21061untilHBR isreleased.Inamultiprocessingsystem,
HBG is output by the ADSP-21061 bus master and is monitored by all others.
CS
I/A
Chip Select.
Asserted by host processor to select the ADSP-21061.
REDY
O (O/D)
Host Bus Acknowledge.
TheADSP-21061deassertsREDY(low)toaddwaitstatestoanasynchronousaccess
of its internal memory or IOP registers by a host. This pin is an open-drain output (O/D) by default; it can be
programmed in the ADREDY bit of the SYSCON register to be active drive (A/D). REDY will only be output if
the CS and HBR inputs are asserted.
DMAR2–1
I/A
DMA Request 1
(DMA Channel 7) and DMA Request 2 (DMA Channel 6).
DMAG2–1
O/T
DMA Grant 1
(DMA Channel 7) and DMA Grant 2 (DMA Channel 6).
BR6–1
I/O/S
Multiprocessing Bus Requests.
Used by multiprocessing ADSP-21061 processors to arbitrate for bus
mastership. An ADSP-21061 only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and
monitors all others. In a multiprocessor system with less than six ADSP-21061s, the unused BRx pins should
be pulled high; the processor’s own BRx line must not be pulled high or low because it is an output.
ID2–0
O (O/D)
Multiprocessing ID.
Determines which multiprocessing bus request (BR1– BR6) is used by ADSP-21061.
ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc., ID = 000 in single-processor systems. These
lines are a system configuration selection which should be hardwired or changed at reset only.
RPBA
I/S
Rotating Priority Bus Arbitration Select.
When RPBA is high, rotating priority for multiprocessor bus
arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration
selection which must be set to the same value on every ADSP-21061. If the value of RPBA is changed during
system operation, it must be changed in the same CLKIN cycle on every ADSP-21061.
CPA
I/O (O/D)
Core Priority Access.
AssertingitsCPApinallows the coreprocessor of anADSP-21061bus slaveto interrupt
background DMA transfers and gain access to the external bus. CPA is an open-drain output that is
connected to all ADSP-21061s in the system. The CPA pin has an internal 5 k pull-up resistor. If core access
priority is not required in a system, the CPA pin should be left unconnected.
DTx
O
Data Transmit (Serial Ports 0, 1).
Each DT pin has a 50 k internal pull-up resistor.
DRx
I
Data Receive (Serial Ports 0, 1).
Each DR pin has a 50 k internal pull-up resistor.
TCLKx
I/O
Transmit Clock (Serial Ports 0, 1).
Each TCLK pin has a 50 k internal pull-up resistor.
RCLKx
I/O
Receive Clock (Serial Ports 0, 1).
Each RCLK pin has a 50 k internal pull-up resistor.
Table 2. Pin Descriptions (Continued)
Pin
Type
Function
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,
T = Three-State (when SBTS is asserted, or when the ADSP-21061 is a bus slave)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-B31-CY-F2 | CONVERTER MOD DC/DC 12V 50W |
| TAJY156M025RNJ | CAP TANT 15UF 25V 20% 2917 |
| 5717-RC | CHOKE RF HI CURR 500UH 15% RAD |
| VI-B30-CY-F2 | CONVERTER MOD DC/DC 5V 50W |
| MAX6665ASA70+T | IC FAN CNTRL/DRVR 8-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21061KSZ-160 | 功能描述:IC DSP CONTROLLER 1MBIT 240MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21061KSZ-200 | 功能描述:IC DSP CONTROLLER 32BIT 240MQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21061L | 制造商:Analog Devices 功能描述: |
| ADSP-21061LAS-160 | 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2106x SHARC DSP Microcomputer Family |
| ADSP-21061LAS-176 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 44MHz 44MIPS 240-Pin MQFP Tray 制造商:Analog Devices 功能描述:IC MICROCOMPUTER DSP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。