參數(shù)資料
型號(hào)： ADSP-21061KSZ-160
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 30/52頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 1MBIT 240MQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類(lèi)型： 浮點(diǎn)
接口： 同步串行端口（SSP）
時(shí)鐘速率： 40MHz
非易失內(nèi)存： 外部
芯片上RAM： 128kB
電壓 - 輸入/輸出： 5.00V
電壓 - 核心： 5.00V
工作溫度： 0°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 240-BFQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 240-MQFP-EP（32x32）
包裝： 托盤(pán)
Rev. D | Page 36 of 52 | May 2013
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes, DMARx is used to initiate transfers. For
Handshake mode, DMAGx controls the latching or enabling of
data externally. For External Handshake mode, the data transfer
is controlled by the ADDR31–0, RD, WR, SW, PAGE, MS3–0,
ACK, and DMAGx signals. For Paced Master mode, the data
transfer is controlled by ADDR31–0, RD, WR, MS3–0, and
ACK (not DMAG). For Paced Master mode, the Memory Read-
Bus Master, Memory Write-Bus Master, and Synchronous
Read/Write-Bus Master timing specifications for ADDR31–0,
RD, WR, MS3–0, SW, PAGE, DATA47–0, and ACK also apply.
Table 20. DMA Handshake
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tSDRLC
DMARx Low Setup Before CLKIN1
5ns
tSDRHC
DMARx High Setup Before CLKIN1
5ns
tWDR
DMARx Width Low (Nonsynchronous)
6
ns
tSDATDGL
Data Setup After DMAGx Low2
10 + 5DT/8
ns
tHDATIDG
Data Hold After DMAGx High
2
ns
tDATDRH
Data Valid After DMARx High2
16 + 7DT/8
ns
tDMARLL
DMARx Low Edge to Low Edge3
23 + 7DT/8
ns
tDMARH
DMARx Width High
6
ns
Switching Characteristics
tDDGL
DMAGx Low Delay After CLKIN
9 + DT/4
15 + DT/4
ns
tWDGH
DMAGx High Width
6 + 3DT/8
ns
tWDGL
DMAGx Low Width
12 + 5DT/8
ns
tHDGC
DMAGx High Delay After CLKIN
–2 – DT/8
6 – DT/8
ns
tVDATDGH
Data Valid Before DMAGx High4
8 + 9DT/16
ns
tDATRDGH
Data Disable After DMAGx High5
07
ns
tDGWRL
WR Low Before DMAGx Low
0
2
ns
tDGWRH
DMAGx Low Before WR High
10 + 5DT/8 +W
ns
tDGWRR
WR High Before DMAGx High
1 + DT/16
3 + DT/16
ns
tDGRDL
RD Low Before DMAGx Low
0
2
ns
tDRDGH
RD Low Before DMAGx High
11 + 9DT/16 + W
ns
tDGRDR
RD High Before DMAGx High
0
3
ns
tDGWR
DMAGx High to WR, RD, DMAGx Low
5 + 3DT/8 + HI
ns
tDADGH
Address/Select Valid to DMAGx High
17 + DT
ns
tDDGHA
Address/Select Hold after DMAGx High6
–0.5
ns
W = (number of wait states specified in WAIT register) tCK.
HI = tCK (if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
1 Only required for recognition in the current cycle.
2 t
SDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can
be driven tDATDRH after DMARx is brought high.
3 For the ADSP-21061L (3.3 V), this specification is 23.5 + 7DT/8 ns min.
4 t
VDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH =tCK – .25tCCLK –8 +(n×tCK) where n equals
the number of extra cycles that the access is prolonged.
5 See Example System Hold Time Calculation on Page 43 for calculation of hold times given capacitive and dc loads.
6 For the ADSP-21061L (3.3 V), this specification is –1.0 ns min.
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