參數(shù)資料
型號: ADSP-21061LKSZ-160
廠商: Analog Devices Inc
文件頁數(shù): 3/52頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 1MBIT 240MQFP
產(chǎn)品培訓模塊: SHARC Processor Overview
標準包裝: 1
系列: SHARC®
類型: 浮點
接口: 同步串行端口(SSP)
時鐘速率: 40MHz
非易失內(nèi)存: 外部
芯片上RAM: 128kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 240-BFQFP 裸露焊盤
供應商設備封裝: 240-MQFP-EP(32x32)
包裝: 托盤
Rev. D | Page 11 of 52 | May 2013
TFSx
I/O
Transmit Frame Sync (Serial Ports 0, 1).
RFSx
I/O
Receive Frame Sync (Serial Ports 0, 1).
EBOOT
I
EPROM Boot Select.
When EBOOT is high, the ADSP-21061 is configured for booting from an 8-bit EPROM.
When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See the table in the BMS pin
description below. This signal is a system configuration selection that should be hardwired.
LBOOT
I
Link Boot.
Must be tied to GND.
BMS
I/O/T*
Boot Memory Select. Output
: Used as chip select for boot EPROM devices (when EBOOT = 1,
LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that no
booting will occur and that ADSP-21061 will begin executing instructions from external memory. See table
below. This input is a system configuration selection that should be hardwired. *Three-statable only in
EPROM boot mode (when BMS is an output).
EBOOT
LBOOT
BMS
Booting Mode
1
0
Output
EPROM (Connect BMS to EPROM chip select.)
0
1(Input)
Host Processor.
0
0 (Input)
No Booting. Processor executes from external memory.
CLKIN
I
Clock In.
External clock input to the ADSP-21061. The instruction cycle rate is equal to CLKIN. CLKIN may
not be halted, changed, or operated below the minimum specified frequency.
RESET
I/A
Processor Reset.
Resets the ADSP-21061 to a known state and begins program execution at the program
memory location specified by the hardware reset vector address. This input must be asserted (low) at
power-up.
TCK
I
Test Clock (JTAG).
Provides an asynchronous clock for JTAG boundary scan.
TMS
I/S
Test Mode Select (JTAG).
Used to control the test state machine. TMS has a 20 k internal pull-up resistor.
TDI
I/S
Test Data Input (JTAG).
Provides serial data for the boundary scan logic. TDI has a 20 k internal pull-up
resistor.
TDO
O
Test Data Output (JTAG).
Serial scan output of the boundary scan path.
TRST
I/A
Test Reset (JTAG).
Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held
low for proper operation of the ADSP-21061. TRST has a 20 k internal pull-up resistor.
EMU
O
Emulation Status.
Must be connected to the ADSP-21061 EZ-ICE target board connector only. EMU has a
50 k internal pull-up resistor.
ICSA
O
Reserved.
Leave unconnected.
VDD
P
Power Supply
GND
G
Power Supply Return.
(30 pins)
NC
Do Not Connect.
Reserved pins which must be left open and unconnected.
Table 2. Pin Descriptions (Continued)
Pin
Type
Function
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,
T = Three-State (when SBTS is asserted, or when the ADSP-21061 is a bus slave)
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