參數(shù)資料
型號(hào)： ADSP-21061LKSZ-160
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 4/52頁(yè)
文件大小： 0K
描述： IC DSP CONTROLLER 1MBIT 240MQFP
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類(lèi)型： 浮點(diǎn)
接口： 同步串行端口（SSP）
時(shí)鐘速率： 40MHz
非易失內(nèi)存： 外部
芯片上RAM： 128kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： 0°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 240-BFQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 240-MQFP-EP（32x32）
包裝： 托盤(pán)
Rev. D | Page 12 of 52 | May 2013
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JTAG
test access port of the ADSP-2106x to monitor and control the
target board processor during emulation. The EZ-ICE probe
requires the ADSP-2106x’s CLKIN, TMS, TCK, TDI, TDO, and
GND signals be made accessible on the target system via a
14-pin connector (a 2-row, 7-pin strip header) such as that
shown in Figure 5. The EZ-ICE probe plugs directly onto this
connector for chip-on-board emulation. You must add this con-
nector to your target board design if you intend to use the
ADSP-2106x EZ-ICE. The total trace length between the EZ-
ICE connector and the farthest device sharing the EZ-ICE JTAG
pin should be limited to 15 inches maximum for guaranteed
operation. This length restriction must include EZ-ICE JTAG
signals that are routed to one or more ADSP-2106x devices, or a
combination of ADSP-2106x devices and other JTAG devices
on the chain.
The 14-pin, 2-row pin strip header is keyed at the Pin 3 loca-
tion—Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inches in length. Pin spacing
should be 0.1 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie, and Samtec. The BTMS, BTCK,
BTRST, and BTDI signals are provided so that the test access
port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins as shown in
Figure 5. If you are not going to use the test access port for
board testing, tie BTRST to GND and tie or pull up BTCK to
VDD. The TRST pin must be asserted (pulsed low) after power-
up (through BTRST on the connector) or held low for proper
operation of the ADSP-2106x. None of the Bxxx pins (Pins 5, 7,
9, and 11) are connected on the EZ-ICE probe.
The JTAG signals are terminated on the EZ-ICE probe as shown
Figure 6 shows JTAG scan path connections for systems that
contain multiple ADSP-2106x processors.
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform oper-
ations such as starting, stopping, and single-stepping multiple
ADSP-2106xs in a synchronous manner. If you do not need
these operations to occur synchronously on the multiple proces-
sors, simply tie Pin 4 of the EZ-ICE header to ground.
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the multiple
ADSP-21061 processors and the CLKIN pin on the EZ-ICE
header must be minimal. If the skew is too large, synchronous
operations may be off by one or more cycles between proces-
sors. For synchronous multiprocessor operation TCK, TMS,
CLKIN, and EMU should be treated as critical signals in terms
of skew, and should be laid out as short as possible on your
board. If TCK, TMS, and CLKIN are driving a large number of
ADSP-21061s (more than eight) in your system, then treat them
as a “clock tree” using multiple drivers to minimize skew. (See
Figure 7 below and “JTAG Clock Tree” and “Clock Distribu-
tion” in the “High Frequency Design Considerations” section of
the ADSP-2106x SHARC User’s Manual.)
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termina-
tion on TCK and TMS. TDI, TDO, EMU, and TRST are not
critical signals in terms of skew.
Figure 5. Target Board Connector For ADSP-2106x EZ-ICE Emulator
(Jumpers in Place)
TOP VIEW
13
14
11
12
910
9
7
8
56
3
4
12
EMU
GND
TMS
TCK
TRST
TDI
TDO
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
Table 3. Core Instruction Rate/CLKIN Ratio Selection
Signal
Termination
TMS
Driven Through 22 Resistor (16 mA Driver)
TCK
Driven at 10 MHz Through 22 Resistor (16 mA
Driver)
TRST1
1 TRST is driven low until the EZ-ICE probe is turned on by the emulator at software
startup. After software startup, is driven high.
Active Low Driven Through 22 Resistor (16 mA
Driver) (Pulled Up by On-Chip 20 k Resistor)
TDI
Driven by 22 Resistor (16 mA Driver)
TDO
One TTL Load, Split Termination (160/220)
CLKIN
One TTL Load, Split Termination (160/220)
EMU
Active Low, 4.7 k Pull-Up Resistor, One TTL Load
(Open-Drain Output from the DSP)
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