參數(shù)資料
型號(hào): ADSP-21062LABZ-160
廠商: Analog Devices Inc
文件頁(yè)數(shù): 19/64頁(yè)
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 32BIT 225BGA
產(chǎn)品培訓(xùn)模塊: SHARC Processor Overview
標(biāo)準(zhǔn)包裝: 1
系列: SHARC®
類型: 浮點(diǎn)
接口: 主機(jī)接口,連接端口,串行端口
時(shí)鐘速率: 40MHz
非易失內(nèi)存: 外部
芯片上RAM: 256kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 225-BBGA
供應(yīng)商設(shè)備封裝: 225-PBGA
包裝: 托盤
Rev. F
|
Page 26 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-2106x is the
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD, WR, and
DMAGx strobe timing parameters only applies to asynchronous
access mode.
Table 15. Memory Write—Bus Master
5 V and 3.3 V
Unit
Parameter
Min
Max
Timing Requirements
tDAAK
ACK Delay from Address, Selects1, 2
14 + 7DT/8 + W
ns
tDSAK
ACK Delay from WR Low1
8 + DT/2 + W
ns
Switching Characteristics
tDAWH
Address Selects to WR Deasserted2
17 + 15DT/16 + W
ns
tDAWL
Address Selects to WR Low2
3 + 3DT/8
ns
tWW
WR Pulse Width
12 + 9DT/16 + W
ns
tDDWH
Data Setup Before WR High
7 + DT/2 + W
ns
tDWHA
Address Hold After WR Deasserted
0.5 + DT/16 + H
ns
tDATRWH
Data Disable After WR Deasserted3
1 + DT/16 + H
6 + DT/16 + H
ns
tWWR
WR High to WR, RD, DMAGx Low
8 + 7DT/16 + H
ns
tDDWR
Data Disable Before WR or RD Low
5 + 3DT/8 + I
ns
tWDE
WR Low to Data Enabled
–1 + DT/16
ns
tSADADC
Address, Selects Setup Before ADRCLK High2
0 + DT/4
ns
W = (number of wait states specified in WAIT register) × tCK.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
1 ACK delay/setup: user must meet tDAAK or tDSAK or synchronous specification tSAKC for deassertion of ACK (low), all three specifications must be met for assertion of ACK
(High).
2 The falling edge of MSx, SW, BMS is referenced.
3 See Example System Hold Time Calculation on Page 47 for calculation of hold times given capacitive and dc loads.
Figure 15. Memory Write—Bus Master
RD, DMAG
ACK
DATA
WR
ADDRESS
MSx, SW
BMS
tWW
tSADADC
tDAAK
tWWR
ADRCLK
(OUT)
tDWHA
tDSAK
tDAWL
tWDE
tDDWR
tDATRWH
tDDWH
tDAWH
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