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參數(shù)資料
| 型號： | ADSP-21062LKSZ-160 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 62/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 2MBIT 240MQFP |
| 產(chǎn)品培訓(xùn)模塊： | SHARC Processor Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | 主機(jī)接口，連接端口，串行端口 |
| 時(shí)鐘速率： | 40MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 256kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BFQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 240-MQFP-EP（32x32） |
| 包裝： | 托盤 |
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ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Rev. F
|
Page 7 of 64
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March 2008
DMA Controller
The ADSP-2106x’s on-chip DMA controller allows zero-over-
head data transfers without processor intervention. The DMA
controller operates independently and invisibly to the processor
core, allowing DMA operations to occur while the core is simul-
taneously executing its program instructions.
DMA transfers can occur between the ADSP-2106x’s internal
memory and external memory, external peripherals, or a host
processor. DMA transfers can also occur between the ADSP-
2106x’s internal memory and its serial ports or link ports. DMA
transfers between external memory and external peripheral
devices are another option. External bus packing to 16-,
32-, or 48-bit words is performed during DMA transfers.
Ten channels of DMA are available on the ADSP-2106x—two
via the link ports, four via the serial ports, and four via the
processor’s external port (for either host processor, other
ADSP-2106xs, memory, or I/O transfers). Four additional link
port DMA channels are shared with Serial Port 1 and the exter-
nal port. Programs can be downloaded to the ADSP-2106x
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA request/grant lines
(DMAR1–2, DMAG1–2). Other DMA features include inter-
rupt generation upon completion of DMA transfers and DMA
chaining for automatic linked DMA transfers.
Multiprocessing
The ADSP-2106x offers powerful features tailored to multipro-
cessor DSP systems. The unified address space (see Figure 4)
allows direct interprocessor accesses of each ADSP-2106x’s
internal memory. Distributed bus arbitration logic is included
on-chip for simple, glueless connection of systems containing
up to six ADSP-2106xs and a host processor. Master processor
changeover incurs only one cycle of overhead. Bus arbitration is
selectable as either fixed or rotating priority. Bus lock allows
indivisible read-modify-write sequences for semaphores. A vec-
tor interrupt is provided for interprocessor commands. Maxi-
mum throughput for interprocessor data transfer is
240M bytes/s over the link ports or external port. Broadcast
writes allow simultaneous transmission of data to all
ADSP-2106xs and can be used to implement reflective
semaphores.
Figure 4. Memory Map
0x0004 0000
0x0010 0000
0x0008 0000
0x0018 0000
0x0012 0000
0x0028 0000
0x0038 0000
0x0000 0000
0x0002 0000
0x0040 0000
BANK 1
MS0
BANK 2
MS1
BANK 3
MS2
MS3
IOP REGISTERS
SHORT WORD ADDRESSING
(16-BIT DATA WORDS)
NORMAL WORD ADDRESSING
(32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS)
ADDRESS
BANK 0
SDRAM
(OPTIONAL)
0x0FFF FFFF
NONBANKED
NOTE: BANK SIZES ARE SELECTED BY
MSIZE BITS IN THE SYSCON REGISTER
0x0030 0000
INTERNAL
MEMORY
SPACE
MULTIPROCESSOR
MEMORY
SPACE
ADDRESS
INTERNAL MEMORY SPACE
WITH ID = 001
0x003F FFFF
EXTERNAL
MEMORY
SPACE
INTERNAL MEMORY SPACE
WITH ID = 010
INTERNAL MEMORY SPACE
WITH ID = 011
INTERNAL MEMORY SPACE
WITH ID = 100
INTERNAL MEMORY SPACE
WITH ID = 101
INTERNAL MEMORY SPACE
WITH ID = 110
BROADCAST WRITE
TO ALL ADSP-21061s
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