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參數(shù)資料
| 型號： | ADSP-21369KBPZ-2A |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/64頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 32BIT 333MHZ 256-BGA |
| 產(chǎn)品培訓(xùn)模塊： | SHARC Processor Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | DAI，DPI |
| 時鐘速率： | 333MHz |
| 非易失內(nèi)存： | ROM（768 kB） |
| 芯片上RAM： | 256kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（27x27） |
| 包裝： | 托盤 |
| 配用： | ADZS-21369-EZLITE-ND - KIT EVAL EZ LITE ADDS-21369 |
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Rev. F
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Page 14 of 64
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October 2013
SDRAS
O/T (pu)1
Pulled high/
driven high
SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other
SDRAM command pins, defines the operation for the SDRAM to perform.
SDCAS
O/T (pu)
Pulled high/
driven high
SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with other
SDRAM command pins, defines the operation for the SDRAM to perform.
SDWE
O/T (pu)
Pulled high/
driven high
SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.
SDCKE
O/T (pu)
Pulled high/
driven high
SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK signal.
For details, see the data sheet supplied with the SDRAM device.
SDA10
O/T (pu)
Pulled high/
driven low
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-
SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.
SDCLK0
O/T
High-Z/driving
SDRAM Clock Output 0. Clock driver for this pin differs from all other clock drivers. See
SDCLK1
O/T
SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple
SDRAM devices, handles the increased clock load requirements, eliminating need of off-
chip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated. Clock driver
for this pin differs from all other clock drivers. See Figure 40 on Page 51.
The SDCLK1 signal is only available on the SBGA package. SDCLK1 is not available on the
LQFP_EP package.
DAI _P20–1
I/O with pro-
grammable
pu2
Pulled high/
pulled high
Digital Applications Interface. These pins provide the physical interface to the DAI SRU.
The DAI SRU configuration registers define the combination of on-chip audiocentric
peripheral inputs or outputs connected to the pin, and to the pin’s output enable. The
configuration registers then determines the exact behavior of the pin. Any input or
output signal present in the DAI SRU may be routed to any of these pins. The DAI SRU
provides the connection from the serial ports (8), the SRC module, the S/PDIF module,
input data ports (2), and the precision clock generators (4), to the DAI_P20–1 pins. Pull-
ups can be disabled via the DAI_PIN_PULLUP register.
DPI _P14–1
I/O with pro-
grammable
Pulled high/
pulled high
Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.
The DPI SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU
provides the connection from the timers (3), SPIs (2), UARTs (2), flags (12) TWI (1), and
general-purpose I/O (9) to the DPI_P14–1 pins. The TWI output is an open-drain output—
so the pins used for I2C data and clock should be connected to logic level 0. Pull-ups can
be disabled via the DPI_PIN_PULLUP register.
TDI
I (pu)
Test Data Input (JTAG). Provides serial data for the boundary scan logic.
TDO
O/T
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TMS
I (pu)
Test Mode Select (JTAG). Used to control the test state machine.
TCK
I
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed
low) after power-up, or held low for proper operation of the processor
TRST
I (pu)
Test Reset(JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after
power-up or held low for proper operation of the processor.
Table 8. Pin Descriptions (Continued)
Name
Type
State During/
After Reset
(ID = 00x)
Description
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