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| 型號： | ADSP-21479KCPZ-1A |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP SHARK 200MHZ 88LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點 |
| 接口： | DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART |
| 時鐘速率： | 200MHz |
| 非易失內(nèi)存： | ROM（4Mb） |
| 芯片上RAM： | 5Mb |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 88-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 88-LFCSP-VQ（12x12） |
| 包裝： | 托盤 |
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Rev. C
|
Page 16 of 76
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July 2013
PIN FUNCTION DESCRIPTIONS
Table 11. Pin Descriptions
Name
Type
State During/
After Reset
Description
ADDR23–0
I/O/T (ipu)
High-Z/driven
low (boot)
External Address. The processor outputs addresses for external memory and
peripherals on these pins. The ADDR pins can be multiplexed to support the
external memory interface address, FLAGS15–8 (I/O) and PWM (O). After reset, all
ADDR pins are in EMIF mode, and FLAG(0–3) pins are in FLAGS mode (default).
When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the ADDR23–4
pins for parallel input data.
DATA15–0
I/O/T (ipu)
High-Z
External Data. The data pins can be multiplexed to support the external memory
interface data (I/O) and FLAGS7–0 (I/O).
AMI_ACK
I (ipu)
Memory Acknowledge. External devices can deassert AMI_ACK (low) to add wait
states to an external memory access. AMI_ACK is used by I/O devices, memory
controllers, or other peripherals to hold off completion of an external memory
access.
MS0–1
O/T (ipu)
High-Z
Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the
corresponding banks of external memory. The MS1-0 lines are decoded memory
address lines that change at the same time as the other address lines. When no
external memory access is occurring the MS1-0 lines are inactive; they are active
however when a conditional memory access instruction is executed, when the
condition evaluates as true.
The MS1 pin can be used in EPORT/FLASH boot mode. For more information on
processor booting, see the ADSP-214xx SHARC Processor Hardware Reference.
AMI_RD
O/T (ipu)
High-Z
AMI Port Read Enable. AMI_RD is asserted whenever the processor reads a word
from external memory.
AMI_WR
O/T (ipu)
High-Z
AMI Port Write Enable. AMI_WR is asserted when the processor writes a word to
external memory.
FLAG0/IRQ0
I/O (ipu)
FLAG[0] INPUT
FLAG0/Interrupt Request0.
FLAG1/IRQ1
I/O (ipu)
FLAG[1] INPUT
FLAG1/Interrupt Request1.
FLAG2/IRQ2/MS2
I/O (ipu)
FLAG[2] INPUT
FLAG2/Interrupt Request2/Memory Select2. This pin is multiplexed with MS2
in the 196-ball BGA package only.
FLAG3/TMREXP/MS3
I/O (ipu)
FLAG[3] INPUT
FLAG3/Timer Expired/Memory Select3. This pin is multiplexed with MS3 in the
196-ball BGA package only.
The following symbols appear in the Type column of Table 11: A = asynchronous, I =input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors
cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 kΩ to 63 kΩ. The
range of an ipd resistor can be 31 kΩ to 85 kΩ. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical conditions
the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.
Not all pins are available in the 88-lead LFCSP_VQ and 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 62 on
Page 70.
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