參數(shù)資料
型號： ADSP-21479KCPZ-1A
廠商： Analog Devices Inc
文件頁數(shù)： 9/76頁
文件大?。?/td> 0K
描述： IC DSP SHARK 200MHZ 88LFCSP
標準包裝： 1
系列： SHARC®
類型： 浮點
接口： DAI，DPI，EBI/EMI，I²C，SPI，SPORT，UART/USART
時鐘速率： 200MHz
非易失內存： ROM（4Mb）
芯片上RAM： 5Mb
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 88-VFQFN 裸露焊盤，CSP
供應商設備封裝： 88-LFCSP-VQ（12x12）
包裝： 托盤
Rev. C
|
Page 17 of 76
|
July 2013
SDRAS
O/T (ipu)
High-Z/
driven high
SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with
other SDRAM command pins, defines the operation for the SDRAM to perform.
SDCAS
O/T (ipu)
High-Z/
driven high
SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction
with other SDRAM command pins, defines the operation for the SDRAM to
perform.
SDWE
O/T (ipu)
High-Z/
driven high
SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.
SDCKE
O/T (ipu)
High-Z/
driven high
SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK
signal. For details, see the data sheet supplied with the SDRAM device.
SDA10
O/T (ipu)
High-Z/
driven high
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-
SDRAM accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM
accesses.
SDDQM
O/T (ipu)
High-Z/
driven high
DQM Data Mask. SDRAM input mask signal for write accesses and output enable
signal for read accesses. Input data is masked when DQM is sampled high during
a write cycle. The SDRAM output buffers are placed in a High-Z state when DQM
is sampled high during a read cycle. SDDQM is driven high from reset de-assertion
until SDRAM initialization completes. Afterwards, it is driven low irrespective of
whether any SDRAM accesses occur or not.
SDCLK
O/T (ipd)
High-Z/
driving
SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers.
See Figure 47 on Page 65. For models in the 100-lead package, the SDRAM
interface should be disabled to avoid unnecessary power switching by setting the
DSDCTL bit in SDCTL register. For more information, see the ADSP-214xx SHARC
Processor Hardware Reference.
DAI _P20–1
I/O/T (ipu)
High-Z
Digital Applications Interface. These pins provide the physical interface to the
DAI SRU. The DAI SRU configuration registers define the combination of on-chip
audio-centric peripheral inputs or outputs connected to the pin and to the pin’s
output enable. The configuration registers of these peripherals then determines
the exact behavior of the pin. Any input or output signal present in the DAI SRU
may be routed to any of these pins.
DPI _P14–1
I/O/T (ipu)
High-Z
Digital Peripheral Interface. These pins provide the physical interface to the DPI
SRU. The DPI SRU configuration registers define the combination of on-chip
peripheral inputs or outputs connected to the pin and to the pin's output enable.
The configuration registers of these peripherals then determine the exact
behavior of the pin. Any input or output signal present in the DPI SRU may be
routed to any of these pins.
WDT_CLKIN
I
Watch Dog Timer Clock Input. This pin should be pulled low when not used.
WDT_CLKO
O
Watch Dog Resonator Pad Output.
WDTRSTO
O (ipu)
Watch Dog Timer Reset Out.
Table 11. Pin Descriptions (Continued)
Name
Type
State During/
After Reset
Description
The following symbols appear in the Type column of Table 11: A = asynchronous, I =input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors
cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 kΩ to 63 kΩ. The
range of an ipd resistor can be 31 kΩ to 85 kΩ. The three-state voltage of ipu pads will not reach to full the VDD_EXT level; at typical conditions
the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins.
Not all pins are available in the 88-lead LFCSP_VQ and 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 62 on
Page 70.
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