Timing Requirements: tIKW
參數(shù)資料
型號: ADSP-2181BSZ-133
廠商: Analog Devices Inc
文件頁數(shù): 15/32頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 128PQFP
標準包裝: 1
系列: ADSP-21xx
類型: 定點
接口: 同步串行端口(SSP)
時鐘速率: 33.3MHz
非易失內(nèi)存: 外部
芯片上RAM: 80kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-MQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 738 (CN2011-ZH PDF)
REV. D
ADSP-2181
–22–
Parameter
Min
Max
Unit
IDMA Write, Long Write Cycle
Timing Requirements:
tIKW
IACK Low before Start of Write1
0ns
tIKSU
IAD15–0 Data Setup before
IACK Low2, 3
0.5tCK + 10
ns
tIKH
IAD15–0 Data Hold after
IACK Low2, 3
2ns
Switching Characteristics:
tIKLW
Start of Write to
IACK Low4
1.5tCK
ns
tIKHW
Start of Write to
IACK High
15
ns
NOTES
1Start of Write =
IS Low and IWR Low.
2If Write Pulse ends before
IACK Low, use specifications t
IDSU, tIDH.
3If Write Pulse ends after
IACK Low, use specifications t
IKSU, tIKH .
4This is the earliest time for
IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the User’s Manual.
IAD15–0
DATA
tIKHW
tIKW
IACK
IS
IWR
tIKLW
tIKH
tIKSU
Figure 16. IDMA Write, Long Write Cycle
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