Timing Requirements: tIKR
參數(shù)資料
型號: ADSP-2181BSZ-133
廠商: Analog Devices Inc
文件頁數(shù): 16/32頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 128PQFP
標準包裝: 1
系列: ADSP-21xx
類型: 定點
接口: 同步串行端口(SSP)
時鐘速率: 33.3MHz
非易失內(nèi)存: 外部
芯片上RAM: 80kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-MQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 738 (CN2011-ZH PDF)
ADSP-2181
–23–
REV. D
Parameter
Min
Max
Unit
IDMA Read, Long Read Cycle
Timing Requirements:
tIKR
IACK Low before Start of Read1
0ns
tIRP
Duration of Read
15
ns
Switching Characteristics:
tIKHR
IACK High after Start of Read1
15
ns
tIKDS
IAD15–0 Data Setup before IACK Low
0.5tCK – 10
ns
tIKDH
IAD15–0 Data Hold after End of Read
2
0ns
tIKDD
IAD15–0 Data Disabled after End of Read
2
12
ns
tIRDE
IAD15–0 Previous Data Enabled after Start of Read
0
ns
tIRDV
IAD15–0 Previous Data Valid after Start of Read
15
ns
tIRDH1
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)
3
2tCK – 5
ns
tIRDH2
IAD15–0 Previous Data Hold after Start of Read (PM2)
4
tCK – 5
ns
NOTES
1Start of Read =
IS Low and IRD Low.
2End of Read =
IS High or IRD High.
3DM read or first half of PM read.
4Second half of PM read.
tIRP
tIKR
PREVIOUS
DATA
READ
DATA
tIKHR
tIKDS
tIRDV
tIRDH
tIKDD
tIRDE
tIKDH
IAD15–0
IACK
IS
IRD
Figure 17. IDMA Read, Long Read Cycle
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