參數(shù)資料
型號: ADSP-2185NKSTZ-320
廠商: Analog Devices Inc
文件頁數(shù): 33/48頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 100LQFP
標準包裝: 1
系列: ADSP-21xx
類型: 定點
接口: 主機接口,串行端口
時鐘速率: 80MHz
非易失內(nèi)存: 外部
芯片上RAM: 80kB
電壓 - 輸入/輸出: 1.8V,2.5V,3.3V
電壓 - 核心: 1.80V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
ADSP-218xN
Rev. A
|
Page 39 of 48
|
August 2006
IDMA Read, Short Read Cycle in Short Read Only Mode
Table 26. IDMA Read, Short Read Cycle in Short Read Only Mode
Parameter
1
Min
Max
Unit
Timing Requirements:
tIKR
IACK Low Before Start of Read2
0ns
tIRP
Duration of Read3
10
ns
Switching Characteristics:
tIKHR
IACK High After Start of Read
10
ns
tIKDH
IAD15 – 0 Previous Data Hold After End of Read
0ns
tIKDD
IAD15 – 0 Previous Data Disabled After End of Read
10
ns
tIRDE
IAD15 – 0 Previous Data Enabled After Start of Read
0
ns
tIRDV
IAD15 – 0 Previous Data Valid After Start of Read
10
ns
1 Short Read Only is enabled by setting Bit 14 of the IDMA overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register
or by an external host writing to the register. Disabled by default.
2 Start of Read = IS Low and IRD Low. Previous data remains until end of read.
3 End of Read = IS High or IRD High.
Figure 37. IDMA Read, Short Read Cycle in Short Read Only Mode
tIRP
tIKR
PR E V IO U S
DATA
tIKHR
tIR DV
tIKDD
tIRDE
tIKDH
IAD15–0
IA CK
IS
IRD
LEG EN D :
IM PL IES TH A T
IS AND IR D CAN BE
H E LD INDE FINITE LY BY HO S T
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