參數(shù)資料
型號(hào)： ADSP-2185NKSTZ-320
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 46/48頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 100LQFP
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： 主機(jī)接口，串行端口
時(shí)鐘速率： 80MHz
非易失內(nèi)存： 外部
芯片上RAM： 80kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.80V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤(pán)
ADSP-218xN
Rev. A
|
Page 7 of 48
|
August 2006
such as SCLK, CLKOUT, and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to
incoming interrupts. The one-cycle response time of the stan-
dard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, ADSP-218xN series members
remain in the idle state for up to a maximum of n processor
cycles (n = 16, 32, 64, or 128) before resuming nor-
mal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-218xN series, two serial devices, a byte-wide EPROM,
and optional external program and data overlay memories
(mode-selectable). Programmable wait state generation allows
the processor to connect easily to slow peripheral devices.
ADSP-218xN series members also provide four external inter-
rupts and two serial ports or six external interrupts and one
serial port. Host Memory Mode allows access to the full external
data bus, but limits addressing to a single address bit (A0).
Through the use of external hardware, additional system
peripherals can be added in this mode to generate and latch
address signals.
Figure 2. Basic System Interface
In
ser
t s
yst
em
int
erf
ac
e d
iag
ram
he
re
1/2
CLOCK
OR
CRYSTAL
FL0–2
CLKIN
XTAL
SERIAL
DEVICE
SCLK1
RFS1 OR
IRQ0
TFS1 OR
IRQ1
DT1 OR FO
DR1 OR FI
SPORT1
SERIAL
DEVICE
A0–A21
DATA
BYTE
MEMORY
I/O SPACE
(PERIPHERALS)
DATA
ADDR
DATA
ADDR
2048 LOCATIONS
OVERLAY
MEMORY
TWO 8K
PM SEGMENTS
D23–0
A13–0
D23–8
A10–0
D15–8
D23–16
A13–0
14
24
SCLK0
RFS0
TFS0
DT0
DR0
SPORT0
DATA23–0
ADSP-218xN
CS
1/2
CLOCK
OR
CRYSTAL
CLKIN
XTAL
FL0–2
SERIAL
DEVICE
SCLK1
RFS1 OR
IRQ0
TFS1 OR
IRQ1
DT1 OR FO
DR1 OR FI
SPORT1
16
IDMA PORT
IRD/D6
IS/D4
IAL/D5
IACK/D3
IAD15-0
SERIAL
DEVICE
SCLK0
RFS0
TFS0
DT0
DR0
SPORT0
1
16
A0
DATA23–8
IOMS
BMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
HOST MEMORY MODE
FULL MEMORY MODE
MODE D/PF3
MODE C/PF2
MODE B/PF1
MODE A/PF0
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
MODE D/PF3
MODE C/PF2
MODE B/PF1
MODE A/PF0
WR
RD
SYSTEM
INTERFACE
OR
CONTROLLER
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
IOMS
BMS
PMS
CMS
BR
BG
BGH
PWD
PWDACK
WR
RD
ADSP-218xN
DMS
TWO 8K
DM SEGMENTS
PMS
ADDR13–0
IRQL1/PF6
IWR/D7
相關(guān)PDF資料
PDF描述
AMM15DTAN-S189 CONN EDGECARD 30POS R/A .156 SLD
GSM36DSAN CONN EDGECARD 72POS R/A .156 SLD
GMM36DSAN CONN EDGECARD 72POS R/A .156 SLD
GEM25DSEH-S243 CONN EDGECARD 50POS .156 EYELET
NTV0515MC CONV DC/DC 1W 5VIN 15VOUT DL 3KV
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-2185NKSTZ-3202 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer
ADSP2186 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer
ADSP-2186 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer
ADSP-2186_01 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer
ADSP-2186BCA-160 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*