Timing Requirements: tIK" />
參數資料
型號: ADSP-2186MKSTZ300R
廠商: Analog Devices Inc
文件頁數: 27/40頁
文件大小: 0K
描述: IC DSP CONTROLLER 16BIT 100LQFP
標準包裝: 1
系列: ADSP-21xx
類型: 定點
接口: 主機接口,串行端口
時鐘速率: 75MHz
非易失內存: 外部
芯片上RAM: 40kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 2.50V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 標準包裝
其它名稱: ADSP-2186MKSTZ300RDKR
REV. 0
ADSP-2186M
–33–
Parameter
Min
Max
Unit
IDMA Read, Short Read Cycle
1, 2
Timing Requirements:
tIKR
IACK Low before Start of Read3
0ns
tIRP1
Duration of Read (DM/PM1)
4
10
2tCK – 5ns
tIRP2
Duration of Read (PM2)
5
10
tCK – 5ns
Switching Characteristics:
tIKHR
IACK High after Start of Read3
10
ns
tIKDH
IAD15–0 Data Hold after End of Read
6
0ns
tIKDD
IAD15–0 Data Disabled after End of Read
6
10
ns
tIRDE
IAD15–0 Previous Data Enabled after Start of Read
0
ns
tIRDV
IAD15–0 Previous Data Valid after Start of Read
10
ns
NOTES
1Short Read Only must be disabled in the IDMA Overlay memory mapped register.
2Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.
3Start of Read =
IS Low and IRD Low.
4DM Read or first half of PM Read.
5Second half of PM Read.
6End of Read =
IS High or IRD High.
tIRP
tIKR
PREVIOUS
DATA
tIKHR
tIRDV
tIKDD
tIRDE
tIKDH
IAD15–0
IACK
IS
IRD
Figure 31. IDMA Read, Short Read Cycle
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