參數(shù)資料
型號(hào)： ADSP-2187NBCA-320
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/48頁(yè)
文件大?。?/td> 0K
描述： IC DSP 16BIT 80MHZ 144CSPBGA
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類(lèi)型： 定點(diǎn)
接口： 主機(jī)接口，串行端口
時(shí)鐘速率： 80MHz
非易失內(nèi)存： 外部
芯片上RAM： 160kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.90V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 144-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 144-CSBGA（10x10）
包裝： 托盤(pán)
Rev. A
|
Page 24 of 48
|
August 2006
ADSP-218xN
ESD DIODE PROTECTION
During the power-up sequence of the DSP, differences in the
ramp-up rates and activation time between the two supplies can
cause current to flow in the I/O ESD protection circuitry. To
prevent damage to the ESD diode protection circuitry, Analog
Devices recommends including a bootstrap Schottky diode.
The bootstrap Schottky diode is connected between the core
and I/O power supplies, as shown in Figure 17. It protects the
ADSP-218xN processor from partially powering the I/O supply.
Including a Schottky diode will shorten the delay between the
supply ramps and thus prevent damage to the ESD diode pro-
tection circuitry. With this technique, if the core rail rises ahead
of the I/O rail, the Schottky diode pulls the I/O rail along with
the core rail.
POWER DISSIPATION
To determine total power dissipation in a specific application,
the following equation should be applied for each output: C
VDD
2
f
where:
C = load capacitance.
f = output switching frequency.
Example:
In an application where external data memory is used
and no other outputs are active, power dissipation is calculated
as follows:
Assumptions:
External data memory is accessed every cycle with 50% of
the address pins switching.
External data memory writes occur every other cycle with
50% of the data pins switching.
Each address and data pin has a 10 pF total load at the pin.
Application operates at VDDEXT = 3.3 V and tCK = 30 ns.
Total Power Dissipation = PINT + (C
VDDEXT
2
f)
P INT = internal power dissipation from Figure 22 on Page 27.
(C
VDDEXT
2
f) is calculated for each output, as in the exam-
ple in Table 13.
Figure 17. Dual Voltage Schottky Diode
I/O VOLTAGE
REGULATOR
CORE
VOLTAGE
REGULATOR
VDDEXT
VDDINT
ADSP-218xN
DC INPUT
SOURCE
Table 13. Example Power Dissipation Calculation1
Parameters
No. of Pins
× C (pF)
× VDDEXT
2 (V)
× f (MHz)
PD (mW)
Address
7
10
3.32
20.0
15.25
Data Output, WR
910
3.3
2
20.0
19.59
RD
110
3.3
2
20.0
2.18
CLKOUT, DMS
210
3.3
2
40.0
8.70
45.72
1 Total power dissipation for this example is PINT + 45.72 mW.
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