參數(shù)資料
型號: ADSP-2187NBCA-320
廠商: Analog Devices Inc
文件頁數(shù): 21/48頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 80MHZ 144CSPBGA
標(biāo)準(zhǔn)包裝: 1
系列: ADSP-21xx
類型: 定點
接口: 主機(jī)接口,串行端口
時鐘速率: 80MHz
非易失內(nèi)存: 外部
芯片上RAM: 160kB
電壓 - 輸入/輸出: 1.8V,2.5V,3.3V
電壓 - 核心: 1.90V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 144-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 144-CSBGA(10x10)
包裝: 托盤
Rev. A
|
Page 28 of 48
|
August 2006
ADSP-218xN
Clock Signals and Reset
Table 15. Clock Signals and Reset
Parameter
Min
Max
Unit
Timing Requirements:
tCKI
CLKIN Period
25
40
ns
tCKIL
CLKIN Width Low
8
ns
tCKIH
CLKIN Width High
8
ns
Switching Characteristics:
tCKL
CLKOUT Width Low
0.5tCK – 3
ns
tCKH
CLKOUT Width High
0.5tCK – 3
ns
tCKOH
CLKIN High to CLKOUT High
0
8
ns
Control Signals Timing Requirements:
tRSP
RESET Width Low
5tCK
1
ns
tMS
Mode Setup before RESET High
7
ns
tMH
Mode Hold after RESET High
5
ns
1 Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal oscillator
start-up time).
Figure 26. Clock Signals and Reset
tCKOH
tCKI
tCKIH
tCKIL
tCKH
tCKL
tMH
tMS
CLKIN
CLKOUT
MODE A D
RESET
tRSP
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