參數(shù)資料
型號: ADSP-2187NBSTZ-320
廠商: Analog Devices Inc
文件頁數(shù): 37/48頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 100LQFP
標準包裝: 1
系列: ADSP-21xx
類型: 定點
接口: 主機接口,串行端口
時鐘速率: 80MHz
非易失內存: 外部
芯片上RAM: 160kB
電壓 - 輸入/輸出: 1.8V,2.5V,3.3V
電壓 - 核心: 1.90V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
Rev. A
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Page 42 of 48
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August 2006
ADSP-218xN
BGA PACKAGE PINOUT
The BGA package pinout is shown in Figure 39 and in Table 28.
Pin names in bold text in the table replace the plain text named
functions when Mode C = 1. A + sign separates two functions
when either function can be active for either major I/O mode.
Signals enclosed in brackets [ ] are state bits latched from the
value of the pin at the deassertion of RESET. The multiplexed
pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode
selectable by setting Bit 10 (SPORT1 configure) of the System
Control Register. If Bit 10 = 1, these pins have serial port func-
tionality. If Bit 10 = 0, these pins are the external interrupt and
flag pins. This bit is set to 1 by default upon reset.
Figure 39. 144-Ball BGA Package Pinout (Bottom View)
IRQL0 +PF5
IRQ2 +PF7
NC
CMS
GND
DT 1 /FO
DR1 /FI
GND
NC
EMS
EE
EC LK
IR QE +PF 4
NC
IRQL1 +PF6
IOMS
GND
PMS
DR 0
GND
RESET
ELIN
ELO UT
EINT
NC
BMS
DMS
RF S 0
TF S 1/
IRQ1
SCL K1
ERESET
EBR
BR
EB G
CLK OUT
VDDINT
NC
V DDEX T
SCL K0
D 0 /IAD1 3
RFS 1/
IRQ0
BG
D1/IAD1 4
VDD IN T
CLKIN
GND
VDD IN T
DT 0
TFS0
D 2 /IAD1 5
D3 /
IACK
GND
NC
GND
XTA L
NC
GND
A10 /IAD9
NC
D6 /
IR D
D5 /IAL
NC
D4/
IS
A13 /IAD1 2
NC
A1 2/IAD1 1
A1 1/IAD10
FL1
NC
D7 /
IWR
D1 1
D8
NC
D9
V DDEXT
VDDE XT
A8 /IAD7
FL 0
PF 0
[M O DE A]
FL 2
PF 3
[MO DE D]
GND
VDDEXT
GND
D10
NC
WR
NC
BGH
A9/IAD8
PF 1
[M O DE B]
PF 2
[MO DE C]
NC
D1 3
D1 2
NC
GND
PW DACK
A 6 /IAD5
RD
A5/IAD4
A7/IAD6
PWD
V DDEX T
D2 1
D1 9
D1 5
NC
D14
A 4 /IAD3
A3 /IAD2
GND
NC
GND
V DDEXT
D2 3
D2 0
D1 8
D17
D16
A 2 /IAD1
A1 /IAD0
GND
A0
NC
GND
NC
D2 2
GND
1
2
3
4
5
6
7
8
9
10
11
12
M
L
K
J
H
G
F
E
D
C
B
A
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