參數(shù)資料
型號(hào)： ADSP-21991BBC
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
中文描述： 16-BIT, 150 MHz, OTHER DSP, PBGA196
封裝： MINI, BGA-196
文件頁數(shù)： 29/44頁
文件大?。?/td> 589K
代理商： ADSP-21991BBC
–29–
REV. 0
ADSP-21991
Serial Port Timing
Table 11
and
Figure 12
describe SPORT transmit and receive
operations, while
Figure 13
and
Figure 14
describe SPORT
Frame Sync operations.
Table 11. Serial Port
1, 2
Parameter
External Clock Timing Requirements
t
SFSE
TFS/RFS Setup Before TCLK/RCLK
3
t
HFSE
TFS/RFS Hold After TCLK/RCLK
3
t
SDRE
Receive Data Setup Before RCLK
3
t
HDRE
Receive Data Hold After RCLK
3
t
SCLKW
TCLK/RCLK Width
t
SCLK
TCLK/RCLK Period
Min
Max
Unit
4
4
1.5
4
0.5t
HCLK
–1
2t
HCLK
ns
ns
ns
ns
ns
ns
Internal Clock Timing Requirements
t
SFSI
TFS Setup Before TCLK
4
; RFS Setup Before RCLK
3
t
HFSI
TFS/RFS Hold After TCLK/RCLK
3
t
SDRI
Receive Data Setup Before RCLK
3
t
HDRI
Receive Data Hold After RCLK
3
4
3
2
5
ns
ns
ns
ns
External or Internal Clock Switching Characteristics
t
DFSE
TFS/RFS Delay After TCLK/RCLK (Internally
Generated FS)
4
t
HOFSE
TFS/RFS Hold After TCLK/RCLK (Internally
Generated FS)
4
14
ns
3
ns
External Clock Switching Characteristics
t
DDTE
Transmit Data Delay After TCLK
4
t
HDTE
Transmit Data Hold After TCLK
4
13.4
ns
ns
4
Internal Clock Switching Characteristics
t
DDTI
Transmit Data Delay After TCLK
4
t
HDTI
Transmit Data Hold After TCLK
4
t
SCLKIW
TCLK/RCLK Width
13.4
ns
ns
ns
4
0.5t
HCLK
–3.5
0.5t
HCLK
+2.5
Enable and Three-State
5
Switching Characteristics
t
DTENE
Data Enable from External TCLK
4
t
DDTTE
Data Disable from External TCLK
4
t
DTENI
Data Enable from Internal TCLK
4
t
DDTTI
Data Disable from External TCLK
4
0
12.1
13
13
12
ns
ns
ns
ns
0
External Late Frame Sync Switching Characteristics
t
DDTLFSE
Data Delay from Late External TFS with MCE=1, MFD=0
6, 7
t
DTENLFSE
Data Enable from Late FS or MCE=1, MFD=0
6, 7
10.5
ns
ns
3.5
1
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay
and frame sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.
2
Word selected timing for I
2
S mode is the same as TFS/RFS timing (normal framing only).
3
Referenced to sample edge.
4
Referenced to drive edge.
5
Only applies to SPORT.
6
MCE=1, TFS enable, and TFS valid follow t
DDTENFS
and t
DDTLFSE
.
7
If external RFSD/TFS setup to RCLK/TCLK>0.5t
LSCK
, t
DDTLSCK
and t
DTENLSCK
apply; otherwise, t
DDTLFSE
and t
DTENLFS
apply.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21991BBCZ 功能描述:IC DSP CTLR 16BIT 196CSPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21991BST 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 160MHz 160MIPS 176-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:HIGH PERFORMANCE MIXED SIGNAL DSP - Bulk
ADSP-21991BSTZ 功能描述:IC DSP CONTROLLER 16BIT 176-LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21992BBC 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 150MHz 150MIPS 196-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:MIXED SIGNAL DSP W/32K DM RAM& 16K PMRAM - Bulk
ADSP-21992BST 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 160MHz 160MIPS 176-Pin LQFP 制造商:Analog Devices 功能描述:IC MICROCOMPUTER 16-BIT
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