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參數(shù)資料
| 型號(hào)： | ADSP-BF506BSWZ-3F |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 80/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 400MHZ 1.4V 120LQFP |
| 視頻文件： | Blackfin? BF50x Processor Family |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點(diǎn) |
| 接口： | CAN，EBI/EMI，I²C，IrDA，PPI，SPI，SPORT，UART/USART |
| 時(shí)鐘速率： | 300MHz |
| 非易失內(nèi)存： | 閃存（16MB） |
| 芯片上RAM： | 68kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.29V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 120-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 120-LQFP-EP（14x14） |
| 包裝： | 托盤 |
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Rev. A
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Page 9 of 80
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July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
FLASH MEMORY
The ADSP-BF504F and ADSP-BF506F processors include an
on-chip 32M bit (×16, multiple bank, burst) Flash memory. The
features of this memory include:
Synchronous/asynchronous read
Synchronous burst read mode: 50 MHz
Asynchronous/synchronous read mode
Random access times: 70 ns
Synchronous burst read suspend
Memory blocks
Multiple bank memory array: 4M bit banks
Parameter blocks (top location)
Dual operations
Program erase in one bank while read in others
No delay between read and write operations
Block locking
All blocks locked at power-up
Any combination of blocks can be locked or locked
down
Security
128-bit user programmable OTP cells
64-bit unique device number
Common Flash interface (CFI)
100,000 program/erase cycles per block
Flash memory ships from the factory in an erased state except
for block 0 of the parameter bank. Block 0 of the Flash memory
parameter bank ships from the factory in an unknown state. An
erase operation should be performed prior to programming this
block.
DMA CONTROLLERS
The processor has multiple, independent DMA channels that
support automated data transfers with minimal overhead for
the processor core. DMA transfers can occur between the pro-
cessor’s internal memories and any of its DMA-capable
peripherals. Additionally, DMA transfers can be accomplished
between any of the DMA-capable peripherals and external
devices connected to the external memory interface. DMA-
capable peripherals include the SPORTs, SPI ports, UARTs,
RSI, and PPI. Each individual DMA-capable peripheral has at
least one dedicated DMA channel.
The processor DMA controller supports both one-dimensional
(1-D) and two-dimensional (2-D) DMA transfers. DMA trans-
fer initialization can be implemented from registers or from sets
of parameters called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
Examples of DMA types supported by the processor DMA con-
troller include:
A single, linear buffer that stops upon completion
A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
1-D or 2-D DMA using a linked list of descriptors
2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels, which are provided for transfers
between the various memories of the processor system with
minimal processor intervention. Memory DMA transfers can be
controlled by a very flexible descriptor-based methodology or
by a standard register-based autobuffer mechanism.
WATCHDOG TIMER
The processor includes a 32-bit timer that can be used to imple-
ment a software watchdog function. A software watchdog can
improve system availability by forcing the processor to a known
state through generation of a core and system reset, nonmask-
able interrupt (NMI), or general-purpose interrupt, if the timer
expires before being reset by software. The programmer initial-
izes the count value of the timer, enables the appropriate
interrupt, then enables the timer. Thereafter, the software must
reload the counter before it counts to zero from the pro-
grammed value. This protects the system from remaining in an
unknown state where software, which would normally reset the
timer, has stopped running due to an external noise condition
or software error.
If configured to generate a reset, the watchdog timer resets both
the core and the processor peripherals. After a reset, software
can determine whether the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The timer is clocked by the system clock (SCLK) at a maximum
frequency of fSCLK.
TIMERS
There are nine general-purpose programmable timer units in
the processors. Eight timers have an external pin that can be
configured either as a pulse width modulator (PWM) or timer
output, as an input to clock the timer, or as a mechanism for
measuring pulse widths and periods of external events. These
timers can be synchronized to an external clock input to the sev-
eral other associated PF pins, to an external clock input to the
PPI_CLK input pin, or to the internal SCLK.
The timer units can be used in conjunction with the two UARTs
to measure the width of the pulses in the data stream to provide
a software auto-baud detect function for the respective serial
channels.
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| ADSP-BF506BSWZ-4F | 功能描述:IC DSP 400MHZ 1.4V 120LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF506BSWZ-4FX | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-BF506F | 制造商:Analog Devices 功能描述:LOW POWER BLACKFIN WITH ADVANCED EMBEDDED CONNECTIVITY - Bulk |
| ADSPBF506FBSWZ-ENG | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-BF506KSWZ-3F | 功能描述:IC DSP 12BIT 300MHZ 120LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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