參數(shù)資料
型號(hào): ADSP-BF518BBCZ-4
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 18/68頁(yè)
文件大?。?/td> 0K
描述: IC DSP 16/32B 400MHZ 168CSPBGA
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類(lèi)型: 定點(diǎn)
接口: 以太網(wǎng),I²C,PPI,RSI,SPI,SPORT,UART/USART
時(shí)鐘速率: 400MHz
非易失內(nèi)存: 外部
芯片上RAM: 116kB
電壓 - 輸入/輸出: 1.8V,2.5V,3.3V
電壓 - 核心: 1.30V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 168-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 168-CSPBGA(12x12)
包裝: 托盤(pán)
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Rev. B
|
Page 25 of 68
|
January 2011
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 17 may cause perma-
nent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
When programming OTP memory on the ADSP-BF51x proces-
sor, the V
PPOTP pin/ball must be set to the write value specified in
the Operating Conditions on Page 20. There is a finite amount
of cumulative time that the write voltage may be applied
(dependent on voltage and junction temperature) to V
PPOTP over
the lifetime of the part. Therefore, maximum OTP memory pro-
gramming time for the processor is shown in Table 19.
Table 20 and Table 21 specify the maximum total source/sink
(IOH/IOL) current for a group of pins. Permanent damage can
occur if this value is exceeded. To understand this specification,
if pins PF9, PF8, PF7, PF6, and PF5 from Group 1 in Table 21
table were sourcing or sinking 2 mA each, the total current for
those pins would be 10 mA. This would allow up to 70 mA total
that could be sourced or sunk by the remaining pins in the
group without damaging the device. Note that the VOH and VOL
specifications have separate per-pin maximum current require-
ments as shown in the Electrical Characteristics table.
Table 17. Absolute Maximum Ratings
Parameter
Rating
Internal Supply Voltage (VDDINT)
– 0.3 V to +1.50 V
External (I/O) Supply Voltage
(VDDEXT/VDDMEM)
– 0.3 V to +3.8 V
Input Voltage
1, 2
1 Applies to 100% transient duty cycle. For other duty cycles see Table 18.
2 Applies only when VDDEXT is within specifications. When VDDEXT is outside speci-
fications, the range is VDDEXT ± 0.2.
–0.5 V to +3.6 V
Input Voltage1, 3
3 Applies to signals SCL, SDA.
–0.5 V to +5.5 V
Output Voltage Swing
– 0.5 V to
VDDEXT/VDDMEM+0.5 V
IOH/IOL Current per Pin Group
4
4 For more information, see the information preceding Table 20 and Table 21.
80 mA (max)
Storage Temperature Range
– 65°C to +150°C
Junction Temperature While biased
+110°C
Table 18. Maximum Duty Cycle for Input Transient Voltage1
1 Applies to all signal pins/balls with the exception of CLKIN, XTAL.
VIN Min (V)
2
2 The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the voltages specified and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
VIN Max (V)
Maximum Duty Cycle3
3 Duty cycle refers to the percentage of time the signal exceeds the value for the
100% case. The is equivalent to the measured duration of a single instance of
overshoot or undershoot as a percentage of the period of occurrence.
–0.50
+3.80
100%
–0.70
+4.00
40%
–0.80
+4.10
25%
–0.90
+4.20
15%
–1.00
+4.30
10%
Table 19. Maximum OTP Memory Programming Time
Temperature
VPPOTP
Voltage (V)
25°C
85°C
110°C
6.9
6000 sec
100 sec
25 sec
7.0
2400 sec
44 sec
12 sec
7.1
1000 sec
18 sec
4.5 sec
Table 20. Total Current Pin Groups–VDDMEM Groups
Group
Pins in Group
1
DATA15, DATA14, DATA13, DATA12, DATA11, DATA10
2
DATA9, DATA8, DATA7, DATA6, DATA5, DATA4
3
DATA3, DATA2, DATA1, DATA0, ADDR19, ADDR18
4
ADDR17, ADDR16, ADDR15, ADDR14, ADDR13
5
ADDR12, ADDR11, ADDR10, ADDR9, ADDR8, ADDR7
6
ADDR6, ADDR5, ADDR4, ADDR3, ADDR2, ADDR1
7ABE1, ABE0, SA10, SWE, SCAS, SRAS
8SMS, SCKE, AMS1, ARE, AWE, AMS0, CLKOUT
Table 21. Total Current Pin Groups–VDDEXT Groups
Group
Pins in Group
1
PF9, PF8, PF7, PF6, PF5, PF4, PF3, PF2
2
PF1, PF0, PG15, PG14, PG13, PG12, PG11, PG10
3
PG9, PG8, PG7, PG6, PG5, PG4, PG3, PG2, BMODE0,
BMODE1, BMODE2
4PG1, PG0, TDO, EMU, TDI, TCK, TRST, TMS
5RESET, NMI, CLKBUF
6
PH7, PH6, PH5, PH4, PH3, PH2, PH1, PH0
7
PF15, PF14, PF13, PF12, PF11, SDA, SCL, PF10
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