- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19481 > ADSP-BF536BBCZ-4B (Analog Devices Inc)IC DSP CTLR 16BIT 208CSPBGA PDF資料下載
參數(shù)資料
| 型號： | ADSP-BF536BBCZ-4B |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 67/68頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CTLR 16BIT 208CSPBGA |
| 產(chǎn)品培訓模塊： | Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 標準包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點 |
| 接口： | CAN，SPI，SSP，TWI，UART |
| 時鐘速率： | 400MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 100kB |
| 電壓 - 輸入/輸出： | 2.50V，3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-LFBGA，CSPBGA |
| 供應商設備封裝： | 208-CSPBGA |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁當前第67頁第68頁
Rev. J
|
Page 8 of 68
|
February 2014
Event Control
The Blackfin processor provides a very flexible mechanism to
control the processing of events. In the CEC, three registers are
used to coordinate and control events. Each register is
32 bits wide:
CEC interrupt latch register (ILAT) – Indicates when
events have been latched. The appropriate bit is set when
the processor has latched the event and cleared when the
event has been accepted into the system. This register is
updated automatically by the controller, but it can be writ-
ten only when its corresponding IMASK bit is cleared.
CEC interrupt mask register (IMASK) – Controls the
masking and unmasking of individual events. When a bit is
set in the IMASK register, that event is unmasked and is
processed by the CEC when asserted. A cleared bit in the
IMASK register masks the event, preventing the processor
from servicing the event even though the event may be
latched in the ILAT register. This register can be read or
written while in supervisor mode. (Note that general-pur-
pose interrupts can be globally enabled and disabled with
the STI and CLI instructions, respectively.)
CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but can be read while in supervisor mode.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 3 on Page 7.
SIC interrupt mask register (SIC_IMASK) – Controls the
masking and unmasking of each peripheral interrupt event.
When a bit is set in the register, that peripheral event is
unmasked and is processed by the system when asserted. A
cleared bit in the register masks the peripheral event, pre-
venting the processor from servicing the event.
SIC interrupt status register (SIC_ISR) – As multiple
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.
SIC interrupt wake-up enable register (SIC_IWR) – By
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated. (For more infor-
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC recognizes and queues the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
DMA CONTROLLERS
The Blackfin processors have multiple, independent DMA
channels that support automated data transfers with minimal
overhead for the processor core. DMA transfers can occur
between the processor’s internal memories and any of its DMA-
capable peripherals. Additionally, DMA transfers can be accom-
plished between any of the DMA-capable peripherals and
external devices connected to the external memory interfaces,
including the SDRAM controller and the asynchronous mem-
ory controller. DMA-capable peripherals include the Ethernet
MAC (ADSP-BF536 and ADSP-BF537 only), SPORTs, SPI port,
UARTs, and PPI. Each individual DMA-capable peripheral has
at least one dedicated DMA channel.
The DMA controller supports both one-dimensional (1-D) and
two-dimensional (2-D) DMA transfers. DMA transfer initial-
ization can be implemented from registers or from sets of
parameters called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
Examples of DMA types supported by the DMA controller
include
A single, linear buffer that stops upon completion
A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
1-D or 2-D DMA using a linked list of descriptors
2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page.
DMA Channels 12 and 13
(Memory DMA Stream 0)
IVG13
29
DMA Channels 14 and 15
(Memory DMA Stream 1)
IVG13
30
Software Watchdog Timer
IVG13
31
Port F Interrupt B
IVG13
31
Table 3. System Interrupt Controller (SIC) (Continued)
Peripheral Interrupt Event
Default
Mapping
Peripheral
Interrupt ID
相關PDF資料 |
PDF描述 |
|---|---|
| TAP476M006BRW | CAP TANT 47UF 6.3V 20% RADIAL |
| FSFR1600 | IC FPS POWER SWITCH 9-SIP |
| VI-BTH-CY-F4 | CONVERTER MOD DC/DC 52V 50W |
| VE-20J-CY-F2 | CONVERTER MOD DC/DC 36V 50W |
| TPSE336K025R0300 | CAP TANT 33UF 25V 10% 2917 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-BF536BBCZ4BRL | 功能描述:IC DSP CTLR 16BIT 208CSBGA 制造商:analog devices inc. 系列:Blackfin? 包裝:帶卷（TR） 零件狀態(tài):有效 類型:定點 接口:CAN，SPI，SSP，TWI，UART 時鐘速率:400MHz 非易失性存儲器:外部 片載 RAM:100kB 電壓 - I/O:2.50V，3.30V 電壓 - 內(nèi)核:1.20V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:208-FBGA，CSPBGA 供應商器件封裝:208-CSPBGA（17x17） 標準包裝:1,000 |
| ADSP-BF536SBBC2Z300 | 制造商:Analog Devices 功能描述: |
| ADSP-BF536SBBC2Z400 | 制造商:Analog Devices 功能描述: |
| ADSP-BF537BBC-5A | 功能描述:IC DSP CTLR 16BIT 182CSPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF537BBC-5AV | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。