參數(shù)資料
型號: ADSP-BF547KBCZ-6A
廠商: Analog Devices Inc
文件頁數(shù): 38/100頁
文件大?。?/td> 0K
描述: IC DSP 600MHZ 400CSPBGA
標準包裝: 1
系列: Blackfin®
類型: 定點
接口: SPI,SSP,TWI,UART,USB
時鐘速率: 600MHz
非易失內存: 外部
芯片上RAM: 260kB
電壓 - 輸入/輸出: 2.50V,3.30V
電壓 - 核心: 1.25V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 400-LFBGA,CSPBGA
供應商設備封裝: 400-CSPBGA(17x17)
包裝: 托盤
Rev. C
|
Page 42 of 100
|
February 2010
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
TIMING SPECIFICATIONS
Timing specifications are detailed in this section.
Clock and Reset Timing
Table 25 and Figure 10 describe Clock Input and Reset Timing.
Table 26 and Figure 11 describe Clock Out Timing.
Table 25. Clock Input and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tCKIN
CLKIN Period1, 2, 3, 4
20.0
100.0
ns
tCKINL
CLKIN Low Pulse2
8.0
ns
tCKINH
CLKIN High Pulse2
8.0
ns
tBUFDLAY
CLKIN to CLKBUF Delay
10
ns
tWRST
RESET Asserted Pulsewidth Low
5
11 tCKIN
ns
tRHWFT
RESET High to First HWAIT/HWAITA Transition (Boot Host Wait Mode)
6,7,8,9
6100 tCKIN + 7900 tSCLK
ns
tRHWFT
RESET High to First HWAIT/HWAITA Transition (Reset Output Mode)7,10,11
6100 tCKIN
7000 tCKIN
ns
1 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 16 and Table 13 on Page 35.
2 Applies to PLL bypass mode and PLL non-bypass mode.
3 CLKIN frequency and duty cycle must not change on the fly.
4 If the DF bit in the PLL_CTL register is set, then the maximum tCKIN period is 50 ns.
5 Applies after power-up sequence is complete. See Table 27 and Figure 12 for more information about power-up reset timing.
6 Maximum value not specified due to variation resulting from boot mode selection and OTP memory programming.
7 Values specified assume no invalidation preboot settings in OTP page PBS00L. Invalidating a PBS set will increase the value by 1875 tCKIN (typically).
8 Applies only to boot modes BMODE=1, 2, 4, 6, 7, 10, 11, 14, 15.
9 Use default t
SCLK value unless PLL is reprogrammed during preboot. In case of PLL reprogramming use the new tSCLK value and add PLL_LOCKCNT settle time.
10When enabled by OTP_RESETOUT_HWAIT bit. If regular HWAIT is not required in an application, the OTP_RESETOUT_HWAIT bit in the same page instructs the
HWAIT or HWAITA to simulate reset output functionality. Then an external resistor is expected to pull the signal to the reset level, as the pin itself is in high performance
mode during reset.
11Variances are mainly dominated by PLL programming instructions in PBS00L page and boot code differences between silicon revisions. The earlier is bypassed in boot mode
BMODE = 0. Maximum value assumes PLL programming instructions do not cause the SCLK frequency to decrease.
Figure 10. Clock and Reset Timing
CLKIN
tWRST
tCKIN
tCKINL
tCKINH
tBUFDLAY
RESET
CLKBUF
HWAIT (A)
tRHWFT
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