參數(shù)資料
型號(hào)： ADSP-BF592KCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 15/44頁
文件大?。?/td> 0K
描述： IC DSP CTRLR 64LFCSP
視頻文件： Blackfin? BF592 Introduction
特色產(chǎn)品： Blackfin Embedded Processor
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： 定點(diǎn)
接口： I²C，I²S，IrDA，PPI，SPI，SPORT，UART
時(shí)鐘速率： 400MHz
非易失內(nèi)存： ROM（64 kB）
芯片上RAM： 64kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.29V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
Rev. B
|
Page 22 of 44
|
July 2013
TIMING SPECIFICATIONS
Specifications are subject to change without notice.
Clock and Reset Timing
Table 18 and Figure 7 describe clock and reset operations. Per
the CCLK and SCLK timing specifications in Table 8 to
Table 10, combinations of CLKIN and clock multipliers must
not select core/peripheral clocks in excess of the processor’s
instruction rate.
Table 18. Clock and Reset Timing
VDDEXT 1.8 V Nominal
VDDEXT 2.5 V/3.3 V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
fCKIN
CLKIN Period1, 2, 3, 4
12
50
12
50
MHz
tCKINL
CLKIN Low Pulse1
10
ns
tCKINH
CLKIN High Pulse
10
ns
tWRST
RESET Asserted Pulse Width Low
5
11 × tCKIN
ns
Switching Characteristic
tBUFDLAY
CLKIN to CLKBUF6 Delay
11
10
ns
1 Applies to PLL bypass mode and PLL non bypass mode.
2 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 8 on Page 17 through Table 10
3 The tCKIN period (see Figure 7) equals 1/fCKIN.
4 If the DF bit in the PLL_CTL register is set, the minimum f
CKIN specification is 24 MHz.
5 Applies after power-up sequence is complete. See Table 19 and Figure 8 for power-up reset timing.
6 The ADSP-BF592 processor does not have a dedicated CLKBUF pin. Rather, the EXTCLK pin may be programmed to serve as CLKBUF or CLKOUT. This parameter applies
when EXTCLK is programmed to output CLKBUF.
Figure 7. Clock and Reset Timing
CLKIN
tWRST
tCKIN
tCKINL
tCKINH
tBUFDLAY
RESET
CLKBUF
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