參數(shù)資料
型號： ADSP-TS101SAB2-000
廠商： Analog Devices Inc
文件頁數(shù)： 9/48頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 6MBIT 484 BGA
標準包裝： 1
系列： TigerSHARC®
類型： 定點/浮點
接口： 主機接口，連接端口，多處理器
時鐘速率： 250MHz
非易失內存： 外部
芯片上RAM： 768kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 484-BFBGA
供應商設備封裝： 484-PBGA（19x19）
包裝： 托盤
其它名稱： ADSP-TS101SAB2000
ADSP-TS101S
Rev. C
|
Page 17 of 48
|
May 2009
TDO
O/T
nc
Test Data Output (JTAG). A serial data output of the scan path.
TMS
I (pu
Test Mode Select (JTAG). Used to control the test state machine.
I/A (pu3)
au
Test Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed low after
power-up for proper device operation.
1 See the reference Page 11 to the JTAG emulation technical reference EE-68.
2 The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
3 See Electrical Characteristics on Page 20 for maximum and minimum current consumption for pull-up and pull-down resistances.
Table 10. Pin Definitions—Flags, Interrupts, and Timer
Signal
Type
Term
Description
FLAG3–01
I/O/A (pd2)
nc
FLAG pins. Bidirectional input/output pins can be used as program conditions. Each pin can be
configured individually for input or for output. FLAG3–0 are inputs after power-up and reset.
IRQ3–03
I/A (pu2)
nc
Interrupt Request. When asserted, the DSP generates an interrupt. Each of the IRQ3–0 pins can
be independently set for edge triggered or level sensitive operation. After reset, these pins are
disabled unless the IRQ3–0 strap option is initialized for booting.
TMR0E
O (pd
au
Timer 0 expires. This output pulses for four SCLK cycles whenever timer 0 expires. At reset this
is a strap pin. For additional information, see Table 16 on Page 19.
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
1 The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
2 See Electrical Characteristics on Page 20 for maximum and minimum current consumption for pull-up and pull-down resistances.
3 The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
Table 11. Pin Definitions—Link Ports
Signal
Type
Term
Description
L0DAT7–0
1
I/O
nc
Link0 Data 7–0
L1DAT7–0
I/O
nc
Link1 Data 7–0
L2DAT7–01
I/O
nc
Link2 Data 7–0
L3DAT7–01
I/O
nc
Link3 Data 7–0
L0CLKOUT
O
nc
Link0 Clock/Acknowledge Output
L1CLKOUT
O
nc
Link1 Clock/Acknowledge Output
L2CLKOUT
O
nc
Link2 Clock/Acknowledge Output
L3CLKOUT
O
nc
Link3 Clock/Acknowledge Output
L0CLKIN
I/A
epu
Link0 Clock/Acknowledge Input
L1CLKIN
I/A
epu
Link1 Clock/Acknowledge Input
L2CLKIN
I/A
epu
Link2 Clock/Acknowledge Input
L3CLKIN
I/A
epu
Link3 Clock/Acknowledge Input
L0DIR
O
nc
Link0 Direction. (0 = input, 1 = output)
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
Table 9. Pin Definitions—JTAG Port (Continued)
Signal
Type
Term
Description
Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;
pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state
Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k
to VDD-IO, nc = not connected; au = always used.
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