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參數(shù)資料
| 型號(hào)： | ADT7466ARQZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | dBCool Remote Thermal Controller and Voltage Monitor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | LEAD FREE, MO-137AB, QSOP-16 |
| 文件頁數(shù)： | 23/48頁 |
| 文件大小： | 1269K |
| 代理商： | ADT7466ARQZ-REEL |
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ADT7466
ALERT INTERRUPT BEHAVIOR
The ADT7466 can be polled for status, or an ALERT interrupt
can be generated for out-of-limit conditions. It is important to
note how the ALERT output and status bits behave when
writing interrupt handler software.
Rev. 0 | Page 23 of 48
0
HIGH LIMIT
TEMPERATURE
STICKY
STATUS
BIT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
CLEARED ON READ
(TEMP BELOW LIMIT)
ALERT
Figure 28. ALERT and Status Bit Behavior
Figure 28 shows how the ALERT output and sticky status bits
behave. Once a limit is exceeded, the corresponding status bit is
set to 1. The status bit remains set until the error condition
subsides and the status register is read. This ensures that an out-
of-limit event cannot be missed if software is polling the device
periodically. The ALERT output remains low while a reading is
out-of-limit, until the status register is read. This has implica-
tions on how software handles the interrupt.
Handling Alert Interrupts
To prevent the system from being tied up servicing interrupts, it
is recommended to handle the ALERT interrupt as follows:
1.
Detect the ALERT assertion.
2.
Enter the interrupt handler.
3.
Read the status registers to identify the interrupt source.
4.
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (0x12, 0x13).
5.
Take the appropriate action for a given interrupt source.
6.
Exit the interrupt handler.
7.
Periodically poll the status registers. If the interrupt status
bit has cleared, reset the corresponding interrupt mask bit
to 0. This causes the ALERT output and status bits to
behave as shown in Figure 29.
0
HIGH LIMIT
TEMPERATURE
STICKY
STATUS
BIT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
ALERT
CLEARED ON READ
(TEMP BELOW LIMIT)
INTERRUPT MASK BIT
CLEARED
(ALERT REARMED)
Figure 29. How Masking the Interrupt Source Affects ALERT Output
Masking Interrupt Sources
Interrupt Mask Registers 1 and 2 are located at Addresses 0x12
and 0x13. These registers allow individual interrupt sources to
be masked to prevent ALERT interrupts. Masking an interrupt
source prevents only the ALERT output from being asserted;
the appropriate status bit is set as normal.
Table 22. Interrupt Mask Register 1 (Reg. 0x12)
Bit No.
Name
Description
7
OOL
1 masks ALERT for any alert condition
flagged in Status Register 2.
6
AIN1(TH1)/
REM2
5
AIN2(TH2)
1 masks ALERT for AIN2(TH2).
4
VCC
1 masks ALERT for Vcc.
3
REM1
1 masks ALERT for remote
temperature.
2
LOC
1 masks ALERT for local temperature.
1
FAN1
1 masks ALERT for Fan 1.
0
FAN2
1 masks ALERT for Fan 2.
Table 23. Interrupt Mask Register 2 (Reg. 0x13)
Bit No.
Name
Description
5
THRM2 1 masks ALERT for TH1 open- or short-circuit
errors.
4
THRM1 1 masks TH2 open- or short-circuit errors.
3
D1
1 masks ALERT for Diode 1 open- or short-
circuit errors.
2
D2
1 masks ALERT for Diode 2 open- or short-
circuit errors.
1
PHOT
1 masks ALERT for PROCHOT.
0
OVT
1 masks ALERT for over temperature
(exceeding THERM limits).
1 masks ALERT for AIN1(TH1)/REM2.
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