參數(shù)資料
型號(hào): ADT7517ARQ-REEL7
廠商: ANALOG DEVICES INC
元件分類: 溫度/濕度傳感器
英文描述: SPI/I2C Compatible, Temperature Sensor, Four Channel ADC and Quad Voltage Output DAC
中文描述: DIGITAL TEMP SENSOR-SERIAL, 10BIT(s), 4Cel, RECTANGULAR, SURFACE MOUNT
封裝: MO-137AB, QSOP-16
文件頁(yè)數(shù): 20/44頁(yè)
文件大?。?/td> 1350K
代理商: ADT7517ARQ-REEL7
ADT7516/ADT7517/ADT7519
The ADT7516/ADT7517/ADT7519 power up with averaging
on. This means every channel is measured 16 times and
internally averaged to reduce noise. The conversion time can
also be sped up by turning off the averaging. This is done by
setting Bit C5 of the Control Configuration 2 register
(Address 19h) to 1.
Rev. A | Page 20 of 44
FUNCTION DESCRIPTION—VOLTAGE OUTPUT
Digital-to-Analog Converters
The ADT7516/ADT7517/ADT7519 have four resistor string
DACs fabricated on a CMOS process with resolutions of 12, 10,
and 8 bits, respectively. They contain four output buffer ampli-
fiers and are written to via I
2
C serial interface or SPI serial inter-
face. See the Serial Interface section for more information.
The ADT7516/ADT7517/ADT7519 operate from a single sup-
ply of 2.7 V to 5.5 V, and the output buffer amplifiers provide
rail-to-rail output swing with a slew rate of 0.7 V/μs. All four
DACs share a common reference input, V
REF
-IN. The reference
input is buffered to draw virtually no current from the reference
source because it offers the source a high impedance input. The
devices have a power-down mode in which all DACs may be
turned off completely with a high impedance output.
Each DAC output will not be updated until it receives the
LDAC command. Therefore, while the DAC registers would
have been written to with a new value, this value will not be
represented by a voltage output until the DACs have received
the LDAC command. Reading back from any DAC register
prior to issuing an LDAC command will result in the digital
value that corresponds to the DAC output voltage. Thus, the
digital value written to the DAC register cannot be read back
until after the LDAC command has been initiated. This LDAC
command can be given by either pulling the LDAC pin low
(falling edge loads DACs), setting up Bits D4 and D5 of the
DAC configuration register (Address 1Bh), or using the LDAC
register (Address 1Ch).
When using the LDAC pin to control the DAC register loading,
the low going pulse width should be 20 ns minimum. The
LDAC pin has to go high and low again before the DAC
registers can be reloaded.
Digital-to-Analog Section
The architecture of one DAC channel consists of a resistor
string DAC followed by an output buffer amplifier. The voltage
at the V
REF
-IN pin or the on-chip reference of 2.28 V provides
the reference voltage for the corresponding DAC. Figure 42
shows a block diagram of the DAC architecture. Since the input
coding to the DAC is straight binary, the ideal output voltage is
given by
D
V
V
2
N
REF
OUT
×
=
where:
D
= decimal equivalent of the binary code that is loaded to the
DAC register:
0 to 255 for ADT7519 (8 bits)
0 to 1023 for ADT7517 (10 bits)
0 to 4095 for ADT7516 (12 bits)
N
= DAC resolution
Resistor String
The resistor string section is shown in Figure 43. It is simply a
string of resistors, each of approximately 603 . The digital
code loaded to the DAC register determines at which node on
the string the voltage is tapped off to be fed into the output
amplifier. The voltage is tapped off by closing one of the
switches connecting the string to the amplifier. Because it is a
string of resistors, it is guaranteed monotonic.
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V
OUT
-A
OUTPUT BUFFER
AMPLIFIER
GAIN MODE
(GAIN = 1 OR 2)
REFERENCE
BUFFER
INT V
REF
V
REF
-IN
0
Figure 42. Single DAC Channel Architecture
R
R
R
R
R
TO OUTPUT
AMPLIFIER
0
Figure 43. Resistor String
STRING
DAC A
2.28V
INTERNAL V
REF
V
REF
-IN
STRING
DAC B
STRING
DAC C
STRING
DAC D
0
Figure 44. DAC Reference Buffer Circuit
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