參數(shù)資料
型號(hào)： ADUC7024BCP62
廠商： ANALOG DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 32-BIT, FLASH, 45.5 MHz, MICROCONTROLLER, QCC64
封裝： 9 X 9 MM, MO-220VMMD, LFCSP-64
文件頁(yè)數(shù)： 10/80頁(yè)
文件大?。?/td> 840K
代理商： ADUC7024BCP62
ADuC702x Series
Preliminary Technical Data
PIN FUNCTION DESCRIPTIONS – ADUC7020/ADUC7021/ADUC7022
Table 3. Pin Function Descriptions
Rev. PrB | Page 10 of 80
Pin# ADuC702X
7020
38
39
40
1
2
-
-
-
-
-
7021
37
38
39
40
1
2
3
4
-
-
7022
36
37
38
39
40
1
2
3
4
5
Mnemonic
Type*
Function
ADC0
ADC1
ADC2/CMP0
ADC3/CMP1
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
I
I
I
I
I
I
I
I
I
I
Single-ended or differential Analog input 0
Single-ended or differential Analog input 1
Single-ended or differential Analog input 2 / Comparator Positive Input
Single-ended or differential Analog input 3 / Comparator Negative Input
Single-ended or differential Analog input 4
Single-ended or differential Analog input 5
Single-ended or differential Analog input 6
Single-ended or differential Analog input 7
Single-ended or differential Analog input 8
Single-ended or differential Analog input 9
Ground voltage reference for the ADC. For optimal performance the
analog power supply should be separated from IOGND and DGND
DAC0 Voltage Output / Single-ended or differential Analog input 12
DAC1 Voltage Output / Single-ended or differential Analog input 13
DAC2 Voltage Output / Single-ended or differential Analog input 14
DAC3 Voltage Output / Single-ended or differential Analog input 15
JTAG Test Port Input - Test Mode Select. Debug and download access
JTAG Test Port Input – Test Data In. Debug and download access
Multifunction I/O pin:
Boot Mode. The ADuC702X will enter serial download mode if BM is low
at reset and will execute code if BM is pulled high at reset through a
1kOhm resistor/ General Purpose Input-Output Port 0.0 / Voltage
Comparator Output/ Programmable Logic Array Input Element 7
Multifunction pin: driven low after reset
General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output
/ Programmable Logic Array Output Element 3
JTAG Test Port Input - Test Clock. Debug and download access
JTAG Test Port Output - Test Data Out. Debug and download access
Ground for GPIO. Typically connected to DGND
3.3V Supply for GPIO and input of the on-chip voltage regulator.
2.5V. Output of the on-chip voltage regulator. Must be connected to a
0.47
μ
F capacitor to DGND
Ground for core logic.
General Purpose Input-Output Port 0.3 / JTAG Test Port Input – Test
Reset. Debug and download access / ADC
BUSY
signal output
Reset Input. (active low)
Multifunction I/O pin:
External Interrupt Request 0, active high / General Purpose Input-Output
Port 0.4 / Start conversion input signal for ADC / Programmable Logic
Array Output Element 1
Multifunction I/O pin:
External Interrupt Request 1, active high / General Purpose Input-Output
Port 0.5 / ADC
BUSY
signal / Programmable Logic Array Output Element 2
Serial Port Multiplexed:
General Purpose Input-Output Port 2.0 / UART / Programmable Logic
Array Output Element 5/ Start conversion input signal for ADC
Serial Port Multiplexed:
General Purpose Input-Output Port 0.7 / Output for External Clock signal
/ UART / Programmable Logic Array Output Element 4/ Input to the
3
5
6
GND
REF
S
4
5
6
7
8
9
6
7
-
-
8
9
-
-
-
-
7
8
DAC0/ADC12
DAC1/ADC13
DAC2/ADC14
DAC3/ADC15
TMS
TDI
I/O
I/O
I/O
I/O
I
I
10
10
9
BM/P0.0/CMP
OUT
/P
LAI[7]
I/O
11
11
10
P0.6/T1/MRST/PLA
O[3]
O
12
13
14
15
12
13
14
15
11
12
13
14
TCK
TDO
IOGND
IOV
DD
I
O
S
S
16
16
15
LV
DD
S
17
17
16
DGND
S
18
18
17
P0.3/TRST/ADC
BUSY
I
19
19
18
RST
I
20
20
19
IRQ0/P0.4/CONV
ST
ART
/PLAO[1]
I/O
21
21
20
IRQ1/P0.5/ADC
BUSY
/PLAO[2]
I/O
22
22
21
P2.0/SPM9/PLAO[
5]/CONV
START
I/O
23
23
22
P0.7/ECLK/SPM8/
PLAO[4]/XCLK
I/O
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