參數(shù)資料
型號: ADUC7128BSTZ126-RL
廠商: Analog Devices Inc
文件頁數(shù): 58/92頁
文件大?。?/td> 0K
描述: IC DAS MCU ARM7 ADC/DDS 64-LQFP
產(chǎn)品培訓模塊: ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
Process Control
Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標準包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: PLA,POR,PWM,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 28
程序存儲器容量: 126KB(63K x 16)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b; D/A 1x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 64-LQFP
包裝: 標準包裝
配用: EVAL-ADUC7128QSPZ-ND - KIT DEV FOR ADUC7128
其它名稱: ADUC7128BSTZ126-RLDKR
ADuC7128/ADuC7129
Rev. 0 | Page 61 of 92
Table 85. COMxSTA1 MMR Bit Designations
Bit
Name
Description
7
DCD
Data Carrier Detect.
6
RI
Ring Indicator.
5
DSR
Data Set Ready.
4
CTS
Clear to Send.
3
DDCD
Delta Data Carrier Detect.
Set automatically if DCD changed state since COMxSTA1 last read.
Cleared automatically by reading COMxSTA1.
2
TERI
Trailing Edge Ring Indicator.
Set if NRI changed from 0 to 1 since COMxSTA1 last read.
Cleared automatically by reading COMxSTA1.
1
DDSR
Delta Data Set Ready.
Set automatically if DSR changed state since COMxSTA1 last read.
Cleared automatically by reading COMxSTA1.
0
DCTS
Delta Clear to Send.
Set automatically if CTS changed state since COMxSTA1 last read.
Cleared automatically by reading COMxSTA1.
Table 86. COMxDIV2 MMR Bit Designations
Bit
Name
Description
15
FBEN
Fractional Baud Rate Generator Enable Bit.
Set by user to enable the fractional baud rate generator.
Cleared by user to generate baud rate using the standard 450 UART baud rate generator.
14:13
RSVD
Reserved.
12:11
FBM[1 to 0]
M, if FBM = 0, M = 4 (see the Using the Fractional Divider section).
10:0
FBN[10 to 0]
N (see the Using the Fractional Divider section).
Network Addressable UART Mode
This mode allows connecting the MicroConverter on a 256-node
serial network, either as a hardware single master or via software
in a multimaster network. Bit 7 of COMxIEN1 (ENAM bit)
must be set to enable UART in network-addressable mode.
Note that there is no parity check in this mode. The parity bit is
used for address.
Network Addressable UART Register Definitions
Four additional registers, COMxIEN0, COMxIEN1, COMxIID1,
and COMxADR are used only in network addressable UART
mode.
In network address mode, the least significant bit of the
COMxIEN1 register is the transmitted network address control
bit. If set to 1, the device is transmitting an address. If cleared
to 0, the device is transmitting data. For example, the following
master-based code transmits the slave address followed by the data:
COM0IEN1
= 0xE7;
//Setting ENAM, E9BT, E9BR, ETD, NABP
COM0TX = 0xA0;
// Slave address is 0xA0
while(!(0x020==(COM0STA0 & 0x020))){} // wait for adr tx to finish.
COM0IEN1
= 0xE6;
//
Clear NAB bit to indicate Data is coming
COM0TX = 0x55;
// Tx data to slave: 0x55
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