參數(shù)資料
型號(hào)： ADUC7128BSTZ126-RL
廠商： Analog Devices Inc
文件頁數(shù)： 86/92頁
文件大?。?/td> 0K
描述： IC DAS MCU ARM7 ADC/DDS 64-LQFP
產(chǎn)品培訓(xùn)模塊： ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
Process Control
Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： PLA，POR，PWM，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 28
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b; D/A 1x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 64-LQFP
包裝： 標(biāo)準(zhǔn)包裝
配用： EVAL-ADUC7128QSPZ-ND - KIT DEV FOR ADUC7128
其它名稱： ADUC7128BSTZ126-RLDKR
ADuC7128/ADuC7129
Rev. 0 | Page 87 of 92
HARDWARE DESIGN CONSIDERATIONS
POWER SUPPLIES
The ADuC7128/ADuC7129 operational power supply voltage
range is 3.0 V to 3.6 V. Separate analog and digital power supply
pins (AVDD and IOVDD, respectively) allow AVDD to be kept
relatively free of noisy digital signals often present on the system
IOVDD line. In this mode, the part can also operate with split
supplies, that is, using different voltage supply levels for each
supply. For example, the system can be designed to operate with
an IOVDD voltage level of 3.3 V while the AVDD level can be at
3 V, or vice versa, if required. A typical split supply configuration
is shown in Figure 66.
+
ANALOG SUPPLY
+
DIGITAL SUPPLY
AVDD
GNDREF
DACGND
AGND
REFGND
IOVDD
LVDD
PVDD
DACVDD
IOGND
ADuC7128
10F
0.
1
F
0.1F
0.47F
0.1F
0
60
20
-05
6
Figure 66. External Dual Supply Connections
As an alternative to providing two separate power supplies, the
user can help keep AVDD quiet by placing a small series resistor
and/or ferrite bead between AVDD and IOVDD, and then decoupling
AVDD separately to ground. An example of this configuration is
shown in Figure 67. With this configuration, other analog circuitry
(such as op amps or voltage references) can be powered from
the AVDD supply line as well.
+
DIGITAL SUPPLY
AVDD
GNDREF
DACGND
AGND
REFGND
IOVDD
LVDD
PVDD
DACVDD
IOGND
ADuC7128
10F
0.
1
F
0.1F
0.47F
0.1F
BEAD
1.6V
06
02
0-
05
7
Figure 67. External Single Supply Connections
Note that in both Figure 66 and Figure 67, a large value (10 μF)
reservoir capacitor sits on IOVDD and a separate 10 μF capacitor
sits on AVDD. In addition, local small value (0.1 μF) capacitors
are located at each AVDD and IOVDD pin of the chip. As per
standard design practice, be sure to include all of these capaci-
tors and ensure that the smaller capacitors are close to each
AVDD pin with trace lengths as short as possible.
Connect the ground terminal of each of these capacitors directly
to the underlying ground plane. It should also be noted that, at
all times, the analog and digital ground pins on the ADuC7128/
ADuC7129 must be referenced to the same system ground refer-
ence point.
Finally, on the LFCSP package, the paddle on the bottom of the
package should be soldered to a metal plate to provide mechanical
stability. The metal plate should be connected to ground.
Linear Voltage Regulator
The ADuC7128/ADuC7129 require a single 3.3 V supply, but
the core logic requires a 2.5 V supply. An on-chip linear regulator
generates the 2.5 V from IOVDD for the core logic. The LVDD pin
is the 2.5 V supply for the core logic. The DAC logic and PLL logic
also require a 2.5 V supply that must be connected externally from
the LVDD pin to the DACVDD pin and the PVDD pin. An external
compensation capacitor of 0.47 μF must be connected between
LVDD and DGND (as close as possible to these pins) to act as a
tank of charge, as shown in Figure 68. In addition, decoupling
capacitors of 0.1 μF must be placed as close as possible to the
PVDD pin and the DACVDD pin.
LVDD
PVDD
DACVDD
ADuC7128
0.1F
0.47F
06
02
0-
05
8
Figure 68. Voltage Regulator Connections
The LVDD pin should not be used for any other chip. It is also
recommended that the IOVDD have excellent power supply
decoupling to help improve line regulation performance of the
on-chip voltage regulator.
GROUNDING AND BOARD LAYOUT
RECOMMENDATIONS
As with all high resolution data converters, special attention
must be paid to grounding and PC board layout of the design to
achieve optimum performance from the ADCs and DAC.
Although the ADuC7128/ADuC7129 have separate pins for
analog and digital ground (AGND and IOGND), the user must
not tie these to two separate ground planes unless the two ground
planes are connected together very close to the ADuC7128/
ADuC7129, as illustrated in the simplified example of Figure 69a.
In systems where digital and analog ground planes are connected
together somewhere else (for example, at the system power
supply), they cannot be connected again near the ADuC7128/
ADuC7129 because a ground loop results.
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