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| 型號： | ADUC814ARUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 12BIT ADC 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 17 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 6x12b; D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR |
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ADuC814
Rev. A | Page 21 of 72
ADC CIRCUIT INFORMATION
GENERAL OVERVIEW
The ADC block incorporates a 4.05 msec, 6-channel, 12-bit
resolution, single-supply ADC. This block provides the user
with a multichannel multiplexer, track-and-hold amplifier, on-
chip reference, offset calibration features and ADC. All compo-
nents in this block are easily configured via a 3-register SFR
interface.
The ADC consists of a conventional successive-approximation
converter based around a capacitor DAC. The converter accepts
an analog input range of 0 V to VREF. A precision, factory cali-
brated 2.5 V reference is provided on-chip. An external reference
may also be used via the external VREF pin. This external refer-
ence can be in the range 1.0 V to AVDD.
Single or continuous conversion modes can be initiated in
software. In hardware, a convert signal can be applied to an
external pin (CONVST), or alternatively Timer 2 can be config-
ured to generate a repetitive trigger for ADC conversions.
The ADuC814 has a high speed ADC to SPI interface data
capture logic implemented on-chip. Once configured, this logic
transfers the ADC data to the SPI interface without the need for
CPU intervention.
The ADC has six external input channels. Two of the ADC
channels are multiplexed with the DAC outputs, ADC4 with
DAC0, and ADC5 with DAC1. When the DAC outputs are in
use, any ADC conversion on these channels represents the DAC
output voltage. Due care must be taken to ensure that no
external signal is trying to drive these ADC/DAC channels
while the DAC outputs are enabled.
In addition to the six external channels of the ADC, five internal
signals are also routed through the front end multiplexer. These
signals include a temperature monitor, DAC0, DAC1, VREF, and
AGND. The temperature monitor is a voltage output from an
on-chip band gap reference, which is proportional to absolute
temperature. These internal channels can be selected similarly
to the external channels via CS3–CS0 bits in the ADCCON2 SFR.
The ADuC814 is shipped with factory programmed offset and
gain calibration coefficients that are automatically downloaded
to the ADC on a power-on or RESET event, ensuring optimum
ADC performance. The ADC core contains automatic endpoint
self-calibration and system calibration options that allow the
user to overwrite the factory programmed coefficients if desired
and tailor the ADC transfer function to the system in which it is
being used.
ADC TRANSFER FUNCTION
The analog input range for the ADC is 0 V to VREF. For this
range, the designed code transitions occur midway between
successive integer LSB values, i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . .
FS –3/2 LSBs. The output coding is straight binary with 1 LSB =
FS/4096 or 2.5 V/4096 = 0.61 mV when VREF = 2.5 V. The ideal
input/output transfer characteristic for the 0 V to VREF range is
shown in Figure 23.
OUTPUT
CODE
111...111
111...110
111...101
111...100
000...011
000...010
000...001
000...000
0V 1LSB
VOLTAGE INPUT
+FS
1LSB =
FS
4096
02748-A
-030
Figure 23. ADuC814 ADC Transfer Function
ADC Data Output Format
Once configured via the ADCCON1–3 SFRs, the ADC converts
the analog input and provides an ADC 12-bit result word in the
ADCDATAH/L SFRs. The ADCDATAL SFR contains the
bottom 8 bits of the 12-bit result. The bottom nibble of the
ADCDATAH SFR contains the top 4 bits of the result, while the
top nibble contains the channel ID of the ADC channel which
has been converted on. This ID corresponds to the channel
selection bits CD3–CD0 in the ADCCON2 SFR. The format of
the ADC 12-bit result word is shown in Figure 24.
CH–ID
TOP 4 BITS
HIGH 4 BITS OF
ADC RESULT WORD
LOW 8 BITS OF THE
ADC RESULT WORD
ADCDATAH SFR
ADCDATAL SFR
02748-A
-031
Figure 24. ADC Result Format
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