參數(shù)資料
型號(hào): ADUC814ARUZ-REEL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 31/72頁(yè)
文件大小: 0K
描述: IC MCU FLASH 12BIT ADC 28TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 16.78MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 17
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x12b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 帶卷 (TR)
配用: EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR
ADuC814
Rev. A | Page 37 of 72
ON-CHIP PLL
The ADuC814 is intended for use with a 32.768 kHz watch
crystal. An on-board PLL locks onto a multiple (512) of this
32.768kHz frequency to provide a stable 16.777216 MHz clock
for the system. The core can operate at this frequency or at
binary submultiples of it to allow power saving in cases where
maximum core performance is not required. The default core
clock is the PLL clock divided by 8 (2CD = 23) or 2.097152 MHz.
The PLL is controlled via the PLLCON special function register.
PLLCON
PLL Control Register
SFR Address
D7H
Power-On Default
03H
Bit Addressable
No
OSC_PD
LOCK
---
FINT
CD2
CD1
CD0
Table 13. PLLCON SFR Bit Designations
Bit No.
Name
Description
7
OSC_PD
Oscillator Power-Down Bit.
Set by the user to halt the 32 kHz oscillator in power-down mode.
Cleared by the user to enable the 32 kHz oscillator in power-down mode. This feature allows the oscillator to
continue clocking the TIC even in power-down mode.
6
LOCK
PLL Lock Bit. This is a read-only bit.
Set automatically at power-on to indicate that the PLL loop is correctly tracking the crystal clock. If the external
crystal becomes subsequently disconnected, the PLL rails and the core halts.
Cleared automatically at power-on to indicate that the PLL is not correctly tracking the crystal clock. This may be due
to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output is 16.78 MHz ± 20%.
5
---
Reserved. Should be written with 0.
4
---
Reserved. Should be written with 0.
3
FINT
Fast Interrupt Response Bit.
Set by the user to enable the response to any interrupt to be executed at the fastest core clock frequency, regardless
of the configuration of the CD2–CD0 bits (see below). Once user code has returned from an interrupt, the core
resumes code execution at the core clock selected by the CD2–CD0 bits.
Cleared by the user to disable the fast interrupt response feature.
2
CD2
CPU (Core Clock) Divider Bits.
1
CD1
This number determines the frequency at which the microcontroller core operates.
0
CD0
CD2
CD1
CD0
Core Clock Frequency (MHz)
0
16.777216
0
1
8.388608
0
1
0
4.194304
0
1
2.097152 (Default Core Clock Frequency)
1
0
1.048576
1
0
1
0.524288
1
0
0.262144
1
0.131072
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