參數(shù)資料
型號: ADUC841
廠商: Analog Devices, Inc.
英文描述: MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU
中文描述: MicroConverter的12位ADC和嵌入式高速DAC的62 - kB的閃存微控制器
文件頁數(shù): 52/88頁
文件大?。?/td> 903K
代理商: ADUC841
ADuC841/ADuC842/ADuC843
POWER SUPPLY MONITOR
As its name suggests, the power supply monitor, once enabled,
monitors the DV
DD
supply on the ADuC841/ADuC842/
ADuC843. It indicates when any of the supply pins drops below
one of two user selectable voltage trip points, 2.93 V and 3.08 V.
For correct operation of the power supply monitor function,
AV
DD
must be equal to or greater than 2.7 V. Monitor function is
controlled via the PSMCON SFR. If enabled via the IEIP2 SFR,
the monitor interrupts the core using the PSMI bit in the
PSMCON SFR. This bit is not cleared until the failing power
supply has returned above the trip point for at least 250 ms.
This monitor function allows the user to save working registers
to avoid possible data loss due to the low supply condition, and
also ensures that normal code execution does not resume until a
safe supply level has been well established. The supply monitor
Rev. 0 | Page 52 of 88
is also protected against spurious glitches triggering the
interrupt circuit.
Note that the 5 V part has an internal POR trip level of 4.5 V,
which means that there are no usable PSM levels on the 5 V
part. The 3 V part has a POR trip level of 2.45 V, allowing all
PSM trip points to be used.
PSMCON
SFR Address
Power-On Default
Bit Addressable
Power Supply Monitor
Control Register
DFH
DEH
No
Table 22. PSMCON SFR Bit Designations
Bit No.
Name
7
----
6
CMPD
Description
Reserved.
DV
DD
Comparator Bit.
This is a read-only bit that directly reflects the state of the DV
DD
comparator.
Read 1 indicates that the DV
DD
supply is above its selected trip point.
Read 0 indicates that the DV
DD
supply is below its selected trip point.
Power Supply Monitor Interrupt Bit.
This bit is set high by the MicroConverter if either CMPA or CMPD is low, indicating low analog or digital supply. The
PSMI bit can be used to interrupt the processor. Once CMPD and/or CMPA return (and remain) high, a 250 ms
counter is started. When this counter times out, the PSMI interrupt is cleared. PSMI can also be written by the user.
However, if either comparator output is low, it is not possible for the user to clear PSMI.
DV
DD
Trip Point Selection Bits.
These bits select the DV
DD
trip point voltage as follows:
TPD1
TPD0
Selected DV
DD
Trip Point (V)
0
0
Reserved
0
1
3.08
1
0
2.93
1
1
Reserved
Reserved.
Reserved.
Power Supply Monitor Enable Bit.
Set to 1 by the user to enable the power supply monitor circuit.
Cleared to 0 by the user to disable the power supply monitor circuit.
5
PSMI
4
3
TPD1
TPD0
2
1
0
----
----
PSMEN
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