參數(shù)資料
型號: ADUC841
廠商: Analog Devices, Inc.
英文描述: MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU
中文描述: MicroConverter的12位ADC和嵌入式高速DAC的62 - kB的閃存微控制器
文件頁數(shù): 71/88頁
文件大?。?/td> 903K
代理商: ADUC841
ADuC841/ADuC842/ADuC843
IEIP2
SFR Address
Power-On Default
Bit Addressable
Rev. 0 | Page 71 of 88
Secondary Interrupt Enable Register
A9H
A0H
No
Table 37. IEIP2 SFR Bit Designations
Bit No.
Name
7
----
6
PTI
5
PPSM
4
PSI
3
----
2
ETI
1
EPSMI
0
ESI
Description
Reserved.
Priority for time interval interrupt.
Priority for power supply monitor interrupt.
Priority for SPI/I
2
C interrupt.
This bit must contain zero.
Set by the user to enable, or cleared to disable time interval counter interrupts.
Set by the user to enable, or cleared to disable power supply monitor interrupts.
Set by the user to enable, or cleared to disable SPI or I
2
C serial port interrupts.
Interrupt Priority
The interrupt enable registers are written by the user to enable
individual interrupt sources, while the interrupt priority regis-
ters allow the user to select one of two priority levels for each
interrupt. An interrupt of a high priority may interrupt the
service routine of a low priority interrupt, and if two interrupts
of different priority occur at the same time, the higher level
interrupt is serviced first. An interrupt cannot be interrupted by
another interrupt of the same priority level. If two interrupts of
the same priority level occur simultaneously, a polling sequence
is observed as shown in Table 38.
Table 38. Priority within an Interrupt Level
Source
Priority
Description
PSMI
1 (Highest)
Power Supply Monitor Interrupt.
WDS
2
Watchdog Timer Interrupt.
IE0
2
External Interrupt 0.
ADCI
3
ADC Interrupt.
TF0
4
Timer/Counter 0 Interrupt.
IE1
5
External Interrupt 1.
TF1
6
Timer/Counter 1 Interrupt.
ISPI/I2CI
7
SPI Interrupt/I
2
C Interrupt.
RI + TI
8
Serial Interrupt.
TF2 + EXF2
9
Timer/Counter 2 Interrupt.
TII
11(Lowest)
Time Interval Counter Interrupt.
Interrupt Vectors
When an interrupt occurs, the program counter is pushed onto
the stack, and the corresponding interrupt vector address is
loaded into the program counter. The interrupt vector addresses
are shown in Table 39.
Table 39. Interrupt Vector Addresses
Source
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
ADCI
ISPI/I2CI
PSMI
TII
WDS
Vector Address
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
0053H
005BH
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