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參數(shù)資料
| 型號(hào)： | ADUC842BCPZ8-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 55/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8KB FLASH ADC/DAC 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | DMA，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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ADuC841/ADuC842/ADuC843
Rev. 0 | Page 59 of 88
MOSI is shared with P3.3 and, as such, has the same
configuration as the one shown in Figure 61.
MCO
I2C M
Q3
Q4
SCLOCK
PIN
Q2
Q1
(OFF)
DVDD
50ns GLITCH
REJECTION FILTER
SPE = 0 (I2C ENABLE)
HARDWARE I2C
(SLAVE ONLY)
SFR
BITS
03260-0-062
Figure 63. SCLOCK Pin I/O Functional Equivalent in I2C Mode
Q3
Q1
Q2 (OFF)
DVDD
Q4 (OFF)
SDATA/
MOSI
PIN
SPE = 1 (SPI ENABLE)
HARDWARE SPI
(MASTER/SLAVE)
03260-0-097
Figure 64. SDATA/MOSI Pin I/O Functional Equivalent in SPI Mode
Q3
Q4
Q2
Q1
DVDD
MCO
SDATA/
MOSI
PIN
(OFF)
50ns GLITCH
REJECTION FILTER
SPE = 0 (I2C ENABLE)
HARDWARE I2C
(SLAVE ONLY)
SFR
BITS
MCI
MDE
I2C M
03260-0-063
Figure 65. SDATA/MOSI Pin I/O Functional Equivalent in I2C Mode
Read-Modify-Write Instructions
Some 8051 instructions that read a port read the latch while
others read the pin. The instructions that read the latch rather
than the pins are the ones that read a value, possibly change it,
and then rewrite it to the latch. These are called read-modify-
write instructions, which are listed below. When the destination
operand is a port or a port bit, these instructions read the latch
rather than the pin.
Table 27. Read-Write-Modify Instructions
Instruction
Description
ANL
Logical AND, e.g., ANL P1, A
ORL
(Logical OR, e.g., ORL P2, A
XRL
(Logical EX-OR, e.g., XRL P3, A
JBC
Jump if Bit = 1 and clear bit, e.g., JBC P1.1,
LABEL
CPL
Complement bit, e.g., CPL P3.0
INC
Increment, e.g., INC P2
DEC
Decrement, e.g., DEC P2
DJNZ
Decrement and Jump if Not Zero, e.g., DJNZ
P3, LABEL
MOV PX.Y, C1
Move Carry to Bit Y of Port X
CLR PX.Y1
Clear Bit Y of Port X
SETB PX.Y1
Set Bit Y of Port X
1 These instructions read the port byte (all 8 bits), modify the addressed bit,
and then write the new byte back to the latch.
Read-modify-write instructions are directed to the latch rather
than to the pin to avoid a possible misinterpretation of the
voltage level of a pin. For example, a port pin might be used to
drive the base of a transistor. When 1 is written to the bit, the
transistor is turned on. If the CPU then reads the same port bit
at the pin rather than the latch, it reads the base voltage of the
transistor and interprets it as a Logic 0. Reading the latch rather
than the pin returns the correct value of 1.
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