參數(shù)資料
型號： ADUC848BSZ8-5
廠商： Analog Devices Inc
文件頁數(shù)： 12/108頁
文件大?。?/td> 0K
描述： IC MCU FLASH W/16BIT ADC 52MQFP
產(chǎn)品培訓(xùn)模塊： Process Control
標(biāo)準(zhǔn)包裝： 96
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 8KB（8K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x16b; D/A 1x12b，2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 托盤
Data Sheet
ADuC845/ADuC847/ADuC848
Rev. C | Page 11 of 108
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
52 51 50 49 48
43 42 41 40
47 46 45 44
14 15 16 17 18 19 20 21 22 23 24 25 26
1
2
3
4
5
6
7
8
9
10
11
13
12
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
39
38
37
36
35
34
33
32
31
30
29
28
27
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
DV
DD
DGND
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
ALE
PSEN
EA
DAC
RESET
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
DV
DD
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
SCLOCK
(I
2
C)
P1.0/AIN1
P1.1/AIN2
P1.2/AIN3/REFIN2+
P1.3/AIN4/REFIN2–
AVDD
AGND
REFIN–
REFIN+
P1.4/AIN5
P1.5/AIN6
P1.6/AIN7/IEXC1
P1.7/AIN8/IEXC2
AINCOM/DAC
P2.7/PWMCLK
P2.6/PWM1
P2.5/PWM0
P2.4/T2EX
DGND
DVDD
XTAL2
XTAL1
P2.3/SS/T2
P2.2/MISO
P2.1/MOSI
P2.0/SCLOCK (SPI)
SDATA
DGND
04741-002
ADuC845/ADuC847/ADuC848
Figure 2. 52-Lead MQFP Pin Configuration
04741-
003
P1.1/AIN2
P1.2/AIN3/REFIN2+
P1.3/AIN4/REFIN2–
AGND
AVDD
AGND
REFIN–
REFIN+
P1.4/AIN5
P1.5/AIN6
P1.6/AIN7/IEXC1
P1.7/AIN8/IEXC2
AINCOM/DAC
DAC
AI
N9
AI
N10
R
ESET
P
3.
0/
RxD
P
3.
1/
T
xD
P
3
.2
/IN
T0
P
3
.3
/IN
T1
DV
DD
DG
ND
P
3
.4
/T0
P
3
.5
/T1
P
3.
6/
W
R
P
3.
7/
RD
S
CL
K
(
I2
C)
P2.7/PWMCLK
P2.6/PWM1
P2.5/PWM0
P2.4/T2EX
DGND
DVDD
XTAL1
P2.3/SS/T2
P2.2/MISO
P2.1/MOSI
P2.0/SCLOCK (SPI)
SDATA
P
1.
0/
AI
N1
P
0.
7/
AD7
P
0.
6/
AD6
P
0.
5/
AD5
P
0.
4/
AD4
DV
DD
DG
ND
P
0.
3/
AD3
P
0.
2/
AD2
P
0.
1/
AD1
P
0.
0/
AD0
AL
E
PSEN
EA
14
1
2
3
4
5
6
7
8
9
10
11
13
12
15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
43
45
46
47
48
49
50
51
52
53
54
55
56
44
XTAL2
TOP VIEW
(Not to Scale)
ADuC845/ADuC847/
ADuC848
NOTES
1. THE EXPOSED PADDLE MUST BE LEFT UNCONNECTED.
Figure 3. 56-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No:
52-MQFP
Pin No:
56-LFCSP
Mnemonic
Type1
Description
1
56
P1.0/AIN1
I
By power-on default, P1.0/AIN1 is configured as the AIN1 analog input.
AIN1 can be used as a pseudo differential input when used with AINCOM or as
the positive input of a fully differential pair when used with AIN2.
P1.0 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high
or low externally.
2
1
P1.1/AIN2
I
On power-on default, P1.1/AIN2 is configured as the AIN2 analog input.
AIN2 can be used as a pseudo differential input when used with AINCOM or as
the negative input of a fully differential pair when used with AIN1.
P1.1 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high
or low externally.
3
2
P1.2/AIN3/REFIN2+
I
On power-on default, P1.2/AIN3 is configured as the AIN3 analog input.
AIN3 can be used as a pseudo differential input when used with AINCOM or as
the positive input of a fully differential pair when used with AIN4.
P1.2 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high
or low externally. This pin also functions as a second external differential
reference input, positive terminal.
4
3
P1.3/AIN4/REFIN2
I
On power-on default, P1.3/AIN4 is configured as the AIN4 analog input.
AIN4 can be used as a pseudo differential input when used with AINCOM or as
the negative input of a fully differential pair when used with AIN3.
P1.3 has no digital output driver. It can function as a digital input for which 0
must be written to the port bit. As a digital input, this pin must be driven high
or low externally. This pin also functions as a second external differential
reference input, negative terminal.
5
4
AVDD
S
Analog Supply Voltage.
6
5
AGND
S
Analog Ground.
---
6
AGND
S
A second analog ground is provided with the LFCSP version only.
7
REFIN
I
External Differential Reference Input, Negative Terminal.
8
REFIN+
I
External Differential Reference Input, Positive Terminal.
Footnotes at end of table.
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