VAA = 5 V ± 5%, V
參數(shù)資料
型號(hào): ADV7123JSTZ240
廠商: Analog Devices Inc
文件頁(yè)數(shù): 18/24頁(yè)
文件大小: 0K
描述: IC DAC VIDEO TRPL HI SPD 48-LQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
位數(shù): 10
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 3
電壓電源: 單電源
功率耗散(最大): 30mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
輸出數(shù)目和類型: 6 電流,單極
采樣率(每秒): 240M
產(chǎn)品目錄頁(yè)面: 785 (CN2011-ZH PDF)
ADV7123
Rev. D | Page 3 of 24
SPECIFICATIONS
5 V SPECIFICATIONS
VAA = 5 V ± 5%, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted, TJ MAX = 110°C.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions1
STATIC PERFORMANCE
Resolution (Each DAC)
10
Bits
Integral Nonlinearity (BSL)
1
±0.4
+1
LSB
Differential Nonlinearity
1
±0.25
+1
LSB
Guaranteed Monotonic
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Input Current, IIN
1
+1
μA
VIN = 0.0 V or VDD
PSAVE Pull-Up Current
20
μA
Input Capacitance, CIN
10
pF
ANALOG OUTPUTS
Output Current
2.0
26.5
mA
Green DAC, SYNC = high
2.0
18.5
mA
RGB DAC, SYNC = low
DAC-to-DAC Matching
1.0
5
%
Output Compliance Range, VOC
0
1.4
V
Output Impedance, ROUT
100
Output Capacitance, COUT
10
pF
IOUT = 0 mA
Offset Error
0.025
+0.025
% FSR
Tested with DAC output = 0 V
Gain Error2
5.0
+5.0
% FSR
FSR = 17.62 mA
VOLTAGE REFERENCE, EXTERNAL AND
INTERNAL
Reference Range, VREF
1.12
1.235
1.35
V
POWER DISSIPATION
Digital Supply Current3
3.4
9
mA
fCLK = 50 MHz
10.5
15
mA
fCLK = 140 MHz
18
25
mA
fCLK = 240 MHz
Analog Supply Current
67
72
mA
RSET = 560 Ω
8
mA
RSET = 4933 Ω
Standby Supply Current4
2.1
5.0
mA
PSAVE = low, digital, and control inputs at VDD
Power Supply Rejection Ratio
0.1
0.5
%/%
1 Temperature range TMIN to TMAX: 40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
2 Gain error = {(Measured (FSC)/Ideal (FSC) 1) × 100}, where Ideal = VREF /RSET × K × (0x3FFH) and K = 7.9896.
3 Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
4 These maximum/minimum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range.
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