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參數(shù)資料
| 型號： | ADV7123JSTZ240 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/24頁 |
| 文件大小： | 0K |
| 描述： | IC DAC VIDEO TRPL HI SPD 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 30mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 6 電流，單極 |
| 采樣率（每秒）： | 240M |
| 產(chǎn)品目錄頁面： | 785 (CN2011-ZH PDF) |
ADV7123
Rev. D | Page 6 of 24
Parameter1
Min
Typ
Max
Unit
DAC PERFORMANCE
Glitch Impulse
10
pV-sec
DAC-to-DAC Crosstalk3
23
dB
Data Feedthrough4, 5
22
dB
Clock Feedthrough4, 5
33
dB
1 These maximum/minimum specifications are guaranteed by characterization over the 4.75 V to 5.25 V range.
2 Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF.
3 DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
4 Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5 TTL input values are 0 V to 3 V, with input rise/fall times of 3 ns, measured from the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
3.3 V DYNAMIC SPECIFICATIONS
VAA = 3.0 V to 3.6 V1, VREF = 1.235 V, RSET = 680 Ω, CL = 10 pF. All specifications are TA = 25°C, unless otherwise noted, TJ MAX = 110°C.
Table 4.
Parameter
Min
Typ
Max
Unit
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist2
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz
67
dBc
fCLK = 50 MHz; fOUT = 2.51 MHz
67
dBc
fCLK = 50 MHz; fOUT = 5.04 MHz
63
dBc
fCLK = 50 MHz; fOUT = 20.2 MHz
55
dBc
fCLK = 100 MHz; fOUT = 2.51 MHz
62
dBc
fCLK = 100 MHz; fOUT = 5.04 MHz
60
dBc
fCLK = 100 MHz; fOUT = 20.2 MHz
54
dBc
fCLK = 100 MHz; fOUT = 40.4 MHz
48
dBc
fCLK = 140 MHz; fOUT = 2.51 MHz
57
dBc
fCLK = 140 MHz; fOUT = 5.04 MHz
58
dBc
fCLK = 140 MHz; fOUT = 20.2 MHz
52
dBc
fCLK = 140 MHz; fOUT = 40.4 MHz
41
dBc
Double-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz
70
dBc
fCLK = 50 MHz; fOUT = 2.51 MHz
70
dBc
fCLK = 50 MHz; fOUT = 5.04 MHz
65
dBc
fCLK = 50 MHz; fOUT = 20.2 MHz
54
dBc
fCLK = 100 MHz; fOUT = 2.51 MHz
67
dBc
fCLK = 100 MHz; fOUT = 5.04 MHz
63
dBc
fCLK = 100 MHz; fOUT = 20.2 MHz
58
dBc
fCLK = 100 MHz; fOUT = 40.4 MHz
52
dBc
fCLK = 140 MHz; fOUT = 2.51 MHz
62
dBc
fCLK = 140 MHz; fOUT = 5.04 MHz
61
dBc
fCLK = 140 MHz; fOUT = 20.2 MHz
55
dBc
fCLK = 140 MHz; fOUT = 40.4 MHz
53
dBc
Spurious-Free Dynamic Range Within a Window
Single-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span
77
dBc
fCLK = 50 MHz; fOUT = 5.04 MHz; 2 MHz Span
73
dBc
fCLK = 140 MHz; fOUT = 5.04 MHz; 4 MHz Span
64
dBc
Double-Ended Output
fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span
74
dBc
fCLK = 50 MHz; fOUT = 5.00 MHz; 2 MHz Span
73
dBc
fCLK = 140 MHz; fOUT = 5.00 MHz; 4 MHz Span
60
dBc
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