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參數(shù)資料
| 型號(hào)： | AGL030-VQG100 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 30000 GATES, PQFP100 |
| 封裝： | 14 X 14MM, 0.50 MM PITCH, VQFP-100 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 234K |
| 代理商： | AGL030-VQG100 |
IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
10
Produ ct Brief
In addition, every SRAM block has an embedded FIFO
control unit. The control unit allows the SRAM block to
be configured as a synchronous FIFO without using
additional core VersaTiles. The FIFO width and depth are
programmable. The FIFO also features programmable
Almost-Empty (AEMPTY) and Almost-Full (AFULL) flags in
addition to the normal Empty and Full flags. The
embedded FIFO control unit contains the counters
necessary for generation of the read and write address
pointers. The embedded SRAM/FIFO blocks can be
cascaded to create larger configurations.
PLL and Clock Conditioning Circuitry (CCC)
IGLOO devices provide designers with very flexible clock
conditioning capabilities. Each member of the IGLOO
family contains six CCCs. One CCC (center west side) has a
PLL. The AGL030 does not have a PLL.
The six CCC blocks are located at the four corners and the
centers of the east and west sides.
All six CCC blocks are usable; the four corner CCCs and
the east CCC allow simple clock delay operations as well
as clock spine access.
The inputs of the six CCC blocks are accessible from the
FPGA core or from one of several I/O inputs located near
the CCC that have dedicated connections to the CCC
block.
The CCC block has these key features:
Wide input frequency range (fIN_CCC) = 1.5 MHz to
200 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz to
200 MHz
Two programmable delay types for clock skew
minimization
Clock frequency synthesis (for PLL only)
Additional CCC specifications:
Internal phase shift = 0°, 90°, 180°, and 270°.
Output phase shift depends on the output divider
configuration (for PLL only).
Output duty cycle = 50% ± 1.5% or better (for PLL
only)
Low output jitter: worst case < 2.5% × clock period
peak-to-peak period jitter when single global
network used (for PLL only)
Maximum acquisition time = 200 s (for PLL only)
Exceptional tolerance to input period jitter—
allowable input jitter is up to 1.5 ns (for PLL only)
Four
precise
phases;
maximum
misalignment
between adjacent phases of 40 ps × (200 MHz /
fOUT_CCC) (for PLL only)
Global Clocking
IGLOO devices have extensive support for multiple
clocking domains. In addition to the CCC and PLL support
described above, there is a comprehensive global clock
distribution network.
Each VersaTile input and output port has access to nine
VersaNets: six chip (main) and three quadrant global
networks. The VersaNets can be driven by the CCC or
directly accessed from the core via multiplexers (MUXes).
The VersaNets can be used to distribute low-skew clock
signals or for rapid distribution of high fanout nets.
I/Os with Advanced I/O Standards
The IGLOO family of FPGAs features a flexible I/O structure,
supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and
3.3 V).
IGLOO
FPGAs
support
many
different
I/O
standards—single-ended and differential.
The I/Os are organized into banks, with two or four
banks per device. The configuration of these banks
determines the I/O standards supported.
Each I/O module contains several input, output, and
enable
registers.
These
registers
allow
the
implementation of the following:
Single-Data-Rate applications
Double-Data-Rate
applications—DDR
LVDS,
BLVDS,
and
M-LVDS
I/Os
for
point-to-point
communications
IGLOO banks for the AGL250 device and above support
LVPECL, LVDS, BLVDS and M-LVDS. BLVDS and M-LVDS
can support up to 20 loads.
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| AGL060V2-CS121I | 功能描述:IC FPGA 1KB FLASH 60K 121-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
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