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| 型號(hào)： | AGL030V5-FQN48 |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA, 768 CLBS, 30000 GATES, QCC48 |
| 封裝： | QFN-48 |
| 文件頁(yè)數(shù)： | 13/216頁(yè) |
| 文件大?。?/td> | 6519K |
| 代理商： | AGL030V5-FQN48 |
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IGLOO Low-Power Flash FPGAs
v1.4
1 - 7
All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay
operations as well as clock spine access.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only)
Additional CCC specifications:
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output
divider configuration (for PLL only).
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single
global network used (for PLL only)
Maximum acquisition time is 300 s (for PLL only)
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL
only)
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /
fOUT_CCC (for PLL only)
Global Clocking
IGLOO devices have extensive support for multiple clocking domains. In addition to the CCC and
PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three
quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the
core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for
rapid distribution of high-fanout nets.
I/Os with Advanced I/O Standards
The IGLOO family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V,
1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). IGLOO FPGAs support many different I/O
standards—single-ended and differential.
The I/Os are organized into banks, with two or four banks per device. The configuration of these
banks determines the I/O standards supported.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
Single-Data-Rate applications
Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications
IGLOO banks for the AGL250 device and above support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS
and M-LVDS can support up to 20 loads.
Wide Range I/O Support
Actel IGLOO devices support JEDEC-defined wide range I/O operation. IGLOO devices support both
the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2.7 V
to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to
1.575 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components
from the board or move to less costly components with greater tolerances. Wide range eases I/O
bank management and provides enhanced protection from system voltage spikes, while providing
the flexibility to easily run custom voltage applications.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGL030V5-FQNG48 | FPGA, 768 CLBS, 30000 GATES, QCC48 |
| AGL10002-FFG144I | FPGA, 1000000 GATES, 200 MHz, PBGA144 |
| AGL10002-FFG144 | FPGA, 1000000 GATES, 200 MHz, PBGA144 |
| AGL10002-FFG256I | FPGA, 1000000 GATES, 200 MHz, PBGA144 |
| AGL10002-FFG256 | FPGA, 1000000 GATES, 200 MHz, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL030V5-FQNG132 | 制造商:Microsemi Corporation 功能描述:FPGA IGLOO 30K GATES COMM 130NM 1.5V 132QFN - Trays |
| AGL030V5-FQNG144 | 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL030V5-FQNG144ES | 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL030V5-FQNG144I | 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL030V5-FQNG144PP | 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
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