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參數(shù)資料
| 型號： | AGL10002-FGG256I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 200 MHz, PBGA144 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144 |
| 文件頁數(shù)： | 167/204頁 |
| 文件大小： | 2800K |
| 代理商： | AGL10002-FGG256I |
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
A d v an c ed v0 . 1
2-51
Static (idle) Mode
In Static (idle) mode, none of the clock inputs is
switching, and static power is the only power consumed
by the device. This mode can be achieved by switching
off the incoming clocks to the FPGA benefitting from
reduced power consumption. In addition, I/Os draw only
minimal leakage current. In this mode, embedded SRAM,
I/Os, and registers retain their values so the device can
enter and exit this mode just by switching the clocks on
or off.
If the device embedded PLL is used as the clock source,
Static (idle) mode can easily be entered by pulling LOW
the PLL POWERDOWN pin (active low), which will turn
off the PLL.
Flash*Freeze Mode
IGLOO FPGAs offer an ultra-low static power mode to
reduce power consumption while preserving the state of
the registers and SRAM contents, without switching off
any power supplies, inputs, or input clocks.
Flash*Freeze technology enables the user to switch to
Flash*Freeze mode within 1 s, thus simplifying low-
power design implementation. The Flash*Freeze (FF) pin
(active low) is a dedicated pin used to enter or exit
Flash*Freeze mode directly, or the pin can be routed
internally to the FPGA core to allow the user's logic to
decide if and when it is safe to transition to this mode. If
the FF pin is not used, it can be used as a regular I/O,
benefitting from the inherent low power consumption
of the IGLOO devices.
The FF pin has a built-in glitch filter that ensures spurious
glitches are filtered out to prevent entering or exiting
Flash*Freeze mode accidentally.
There are two ways to use Flash*Freeze mode. In
Flash*Freeze type 1, entering and exiting the mode is
exclusively controlled by the assertion and deassertion of
the FF pin. In Flash*Freeze mode type 2, entering and
exiting the mode is controlled by both the FF pin AND
the user-defined LSICC signal available in the ULSICC
macro.
Refer to Table 2-28 for Flash*Freeze (FF) pin and LSICC
signal assertion and deassertion values.
Flash*Freeze Type 1: Control by
Dedicated Flash*Freeze Pin
The device will enter Flash*Freeze mode 1 s after the
dedicated FF pin is asserted, and returns to normal
operation when the FF pin is deasserted (Figure 2-37). In
this mode, FF pin assertion or deassertion is the only
condition
that
determines
entering
or
exiting
Flash*Freeze mode after 1 s. This mode is implemented
by enabling Flash*Freeze mode (default setting) in the
Compile option of the Actel Designer software.
The FF pin threshold voltages are defined by VCCI and the
supported
single-ended
I/O
standard
in
the
corresponding I/O bank. Figure 2-37 shows the concept
of FF pin control in Flash*Freeze mode type 1.
Figure 2-38 on page 2-52 shows the timing diagram for
entering and exiting Flash*Freeze mode type 1.
Table 2-28 Flash*Freeze Mode Type 1 and Type 2 – Signal
Assertion and Deassertion Values
Signal
Assertion Value
Deassertion
Value
Flash*Freeze (FF) pin
Logic '0'
Logic '1'
LSICC signal
Logic '1'
Logic '0'
Notes:
1. The Flash*Freeze (FF) pin is an active low signal and LSICC is
an active high signal.
2. LSICC signal is used only in Flash*Freeze mode type 2.
Figure 2-37 IGLOO Flash*Freeze Mode Type 1 – Controlled by the Flash*Freeze Pin
FF Signal
Flash*Freeze
Mode Control
Flash*Freeze (FF) Pin
Flash*Freeze
Technology
Actel IGLOO
FPGA
Flash*Freeze
Mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGL10002-FGG256 | FPGA, 1000000 GATES, 200 MHz, PBGA144 |
| AGL10002-FGG484I | FPGA, 1000000 GATES, 200 MHz, PBGA484 |
| AGL10002-FGG484 | FPGA, 1000000 GATES, 200 MHz, PBGA484 |
| AGL10005-FFG144I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFG144 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL1000V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS281 | 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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