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參數(shù)資料
| 型號(hào)： | AGL10005-FFG484 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, FBGA-144 |
| 文件頁(yè)數(shù)： | 129/204頁(yè) |
| 文件大?。?/td> | 2800K |
| 代理商： | AGL10005-FFG484 |
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
2- 16
Advanced v0.1
PLL Macro1
The PLL functionality of the clock conditioning block is
supported by the PLL macro. Note that the PLL macro
reference clock uses the CLKA input of the CCC block,
which is only accessible from the global A[0:2] package
pins. Refer to Figure 2-15 on page 2-17 for more
information.
The PLL macro provides five derived clocks (three
independent) from a single reference clock. The PLL
macro also provides power-down input and lock output
signals.
See
for
more
information.
Inputs:
CLKA: selected clock input
POWERDOWN (active low): disables PLLs. The
default state is Powerdown On (active low).
EXTFB: allows an external signal to be compared
to a reference clock in the PLL core's phase
detector
Outputs:
LOCK: indicates that PLL output has locked on the
input reference signal
GLA, GLB, GLC: outputs to respective global
networks
YB, YC: allows output from the CCC to be routed
back to the FPGA core
As previously described, the PLL allows up to five flexible
and independently configurable clock outputs. Figure 2-20
on page 2-21 illustrates the various clock output options
and delay elements.
As illustrated, the PLL supports three distinct output
frequencies from a given input clock. Two of these (GLB
and GLC) can be routed to the B and C global network
access, respectively, and/or routed to the device core (YB
and YC).
There are five delay elements to support phase control
on all five outputs (GLA, GLB, GLC, YB, and YC).
There is also a delay element in the feedback loop that
can be used to advance the clock relative to the
reference clock.
The PLL macro reference clock can be driven by an INBUF*
macro to create a composite macro, where the I/O macro
drives the global buffer (with programmable delay) using a
hardwired connection. In this case, the I/O must be placed
in one of the dedicated global I/O locations.
The PLL macro reference clock can be driven directly
from the FPGA core.
The PLL macro reference clock can also be driven from an
I/O that is routed through the FPGA regular routing
fabric. In this case, users must instantiate a special macro,
PLLINT,
to
differentiate
from
the
hardwired
I/O
connection described earlier.
During power-up, the PLL outputs will toggle around the
maximum frequency of the VCO gear selected. Toggle
frequencies can range from 40 MHz to 250 MHz. This will
continue as long as the clock input (CLKA) is constant
(HIGH or LOW). This can be prevented by LOW assertion
of the POWERDOWN signal.
The visual PLL configuration in SmartGen, part of the
Libero IDE and Designer tools, will derive the necessary
internal divider ratios based on the input frequency and
desired
output
frequencies
selected
by
the
user.
SmartGen also allows the user to select the various delays
and phase shift values necessary to adjust the phases
between the reference clock (CLKA) and the derived
clocks (GLA, GLB, GLC, YB, and YC). SmartGen also allows
the user to select the input clock source. SmartGen
automatically instantiates the special macro, PLLINT,
when needed.
1. The AGL030 device has no CCC, and thus does not include a PLL.
相關(guān)PDF資料 |
PDF描述 |
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| AGL10005-FFGG144I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFGG144 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFGG256I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFGG256 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFGG484I | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL1000V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS281 | 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:IGLOO 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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