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參數(shù)資料
| 型號(hào)： | AGL10005-FFG484I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, FBGA-144 |
| 文件頁(yè)數(shù)： | 144/204頁(yè) |
| 文件大?。?/td> | 2800K |
| 代理商： | AGL10005-FFG484I |
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IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
2- 30
Advanced v0.1
Advanced I/Os
Introduction
IGLOO devices feature a flexible I/O structure, supporting
a range of mixed voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V)
through a bank-selectable voltage. Table 2-12, Table 2-13,
and Table 2-22 on page 2-47 show the voltages and the
compatible I/O standards. I/Os provide programmable
slew rates (except AGL030), drive strengths, and weak
pull-up and pull-down circuits. 3.3 V PCI and 3.3 V PCI-X
are 5 V–tolerant. See the "5 V Input Tolerance" section
on page 2-40 for possible implementations of 5 V
tolerance.
All I/Os are in a known state during power-up, and any
power-up sequence is allowed without current impact.
Refer to the "I/O Power-Up and Supply Voltage
Industrial)" section on page 3-4 for more information.
During power-up, before reaching activation levels, the
I/O input and output buffers are disabled while the weak
pull-up is enabled. Activation levels are described in
I/O Tile
The IGLOO I/O tile provides a flexible, programmable
structure for implementing a large number of I/O
standards. In addition, the registers available in the I/O
tile in selected I/O banks can be used to support high-
performance register inputs and outputs, with register
enable if desired (Figure 2-24 on page 2-34). The
registers can also be used to support the JESD-79C
Double Data Rate (DDR) standard within the I/O
structure (see the "Double Data Rate (DDR) Support"
section on page 2-35 for more information).
As depicted in Figure 2-24 on page 2-34, all I/O registers
share one CLR port. The output register and output
enable register share one CLK port. Refer to the "I/O
Registers" section on page 2-34 for more information.
I/O Banks and I/O Standards Compatibility
I/Os are grouped into I/O voltage banks. There are four I/O
banks on the AGL250 through AGL1000. The AGL030,
AGL060, and AGL125 have two I/O banks. Each I/O voltage
bank has dedicated I/O supply and ground voltages
(VMV/GNDQ for input buffers and VCCI/GND for output
buffers). Because of these dedicated supplies, only I/Os
with compatible standards can be assigned to the same
I/O voltage bank. Table 2-13 shows the required voltage
compatibility values for each of these voltages.
For more information about I/O and global assignments
to I/O banks in a device, refer to the specific pin table for
the device in the "Package Pin Assignments" section on
I/O standards are compatible if their VCCI and VMV values
are identical. VMV and GNDQ are "quiet" input power
supply pins and are not used on AGL030.
In the AGL030 device, all inputs and disabled outputs are
voltage tolerant up to 3.3 V.
Table 2-12 IGLOO Supported I/O Standards
AGL030
AGL060
AGL125
AGL250
AGL600
AGL1000
Single-Ended
LVTTL/LVCMOS 3.3 V, LVCMOS 2.5 V / 1.8 V / 1.5 V,
LVCMOS 2.5/5.0 V
3.3 V PCI/PCI-X
–
Differential
LVPECL, LVDS, BLVDS, M-LVDS
–
Table 2-13 VCCI Voltages and Compatible IGLOO Standards
VCCI and VMV (typical)
Compatible Standards
3.3 V
LVTTL/LVCMOS 3.3, PCI 3.3, PCI-X 3.3 LVPECL
2.5 V
LVCMOS 2.5, LVCMOS 2.5/5.0, LVDS, BLVDS, M-LVDS
1.8 V
LVCMOS 1.8
1.5 V
LVCMOS 1.5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGL10005-FFG484 | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| AGL10005-FFGG144I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFGG144 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFGG256I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FFGG256 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL1000V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS281 | 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:IGLOO 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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