- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄294981 > AGL10005-FFGG484 FPGA, 1000000 GATES, 250 MHz, PBGA484 PDF資料下載
參數(shù)資料
| 型號： | AGL10005-FFGG484 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144 |
| 文件頁數(shù)： | 170/204頁 |
| 文件大小： | 2800K |
| 代理商： | AGL10005-FFGG484 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁當前第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁
IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
2- 54
Advanced v0.1
I/O State in Flash*Freeze Mode
When the device enters Flash*Freeze mode, I/Os will
become tristated. If the weak pull-up or pull-down
feature is used, the I/Os will maintain the configured
weak pull-up or pull-down status. This feature enables
the design to set the I/O state to a certain level that is
determined by the pull-up/-down configuration. For
example, use the output buffer and enable weak pull-
down to drive a signal LOW to an external component
while the IGLOO device is in Flash*Freeze mode.
Table 2-30 shows the I/O pad state based on the
configuration and buffer type.
Note that configuring weak pull-up or pull-down for the
FF pin is not allowed.
Flash*Freeze Mode Design Considerations
Entering Flash*Freeze Mode
The device was designed and optimized to enter
Flash*Freeze mode only when power supplies are
stable. If the device is being powered up while the FF
pin is asserted (Flash*Freeze mode type 1) or both FF
pin and LSICC signal are asserted (Flash*Freeze mode
type 2), the device is expected to enter Flash*Freeze
mode within 5 s after the I/Os and FPGA core have
reached their activation levels.
If the device is already powered up and then the
FF
pin
is
asserted,
the
device
will
enter
Flash*Freeze mode within 1 s (type 1). In
Flash*Freeze mode type 2 operation, entering
Flash*Freeze mode is done within 1 s after both
FF pin and LSICC signal are asserted. Exiting
Flash*Freeze mode is done within 1 s after
deasserting the FF pin only.
If an embedded PLL is used, entering Flash*Freeze
mode will automatically power down the PLL.
The PLL output clocks will stop toggling within
1 s after the assertion of the FF pin in type 1, or
after both FF pin and LSICC signal are asserted in
type 2. At the same time, I/Os will transition into
the state specified in Table 2-30. The user design
must ensure it is safe to enter Flash*Freeze mode.
During Flash*Freeze Mode
Inputs and input clocks to the FPGA can toggle
without any impact on static power consumption,
assuming weak pull-up or pull-down is not
selected.
If weak pull-up or pull-down is selected and the
input is driven to the opposite direction, power
dissipation will occur.
Any
toggling
signals
will
be
charging
and
discharging the package pin capacitance.
Outputs will be tristated, and the output of the
input or bidirectional buffer tied to the internal
logic will be set to logic 1. Refer to Table 2-30 for
more information.
JTAG operations such as JTAG commands, JTAG
bypass, programming and authentication cannot
be executed. The device must exit Flash*Freeze
mode before JTAG commands can be sent.
The FF pin must be externally driven (deasserted)
for the device to stay in Flash*Freeze mode.
The FF pin is still active; i.e., the pin is used to exit
Flash*Freeze mode when deasserted.
Table 2-30 Flash*Freeze Mode (type 1 and type 2)—I/O Pad State
Buffer Type
Internal Weak Pull-Up/-Down
I/O Pad State in Flash*Freeze Mode
Input
Enabled
Weak pull-up/pull-down*
Disabled
Tristate*
Output
Enabled
Weak pull-up/pull-down
Disabled
Tristate
Tristate output buffer
E = 0 (tristate)
N/A
Tristate
E = 1 (output)
N/A
Tristate
Bidirectional
E = 0 (input)
Enabled
Weak pull-up/pull-down*
Disabled
Tristate*
E = 1 (output)
Enabled
Weak pull-up/pull-down
Disabled
Tristate
Note: *Internal core logic driven by this input buffer will be tied to logic 1 as long as the device is in Flash*Freeze mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGL10005-FG144 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FG256I | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FG256 | FPGA, 1000000 GATES, 250 MHz, PBGA144 |
| AGL10005-FG484I | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
| AGL10005-FG484 | FPGA, 1000000 GATES, 250 MHz, PBGA484 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL1000V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS281 | 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA（27X27） |
發(fā)布緊急采購，3分鐘左右您將得到回復。