IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
2- 18
Advanced v0.1
Table 2-3 Available IGLOO I/O Standards within CLKBUF
and CLKBUF_LVDS/LVPECL Macros
CLKBUF Macros
CLKBUF_LVCMOS5
CLKBUF_LVCMOS331
CLKBUF_LVCMOS18
CLKBUF_LVCMOS15
CLKBUF_PCI
CLKBUF_LVDS2
CLKBUF_LVPECL
Notes:
1. By default, the CLKBUF macro uses the 3.3 V LVTTL I/O
2. BLVDS
and
M-LVDS
standards
are
supported
by
CLKBUF_LVDS.
concerning the dynamic PLL.
The AGL030 device does not contain a PLL.
Figure 2-17 CCC/PLL Macro
Note: The CLKDLY macro uses programmable delay element type 2.
Figure 2-18 CLKDLY
OADIV[4:0]*
OAMUX[2:0]*
DLYGLA[4:0]*
OBDIV[4:0]*
OBMUX[2:0]*
DLYYB[4:0]*
DLYGLB[4:0]*
OCDIV[4:0]*
OCMUX[2:0]*
DLYYC[4:0]*
DLYGLC[4:0]*
FINDIV[6:0]*
FBDIV[6:0]*
FBDLY[4:0]*
FBSEL[1:0]*
XDLYSEL*
VCOSEL[2:0]*
CLKA
EXTFB
GLA
LOCK
GLB
YB
GLC
YC
POWERDOWN
CLKDLY
CLK
GL
DLYGL[4:0]